View NT5TU32M16EG-BE_9115992.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 1 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved commercial , industrial and automotive ddr2 512 mb sdram ? jedec ddr2 compliant - double - data rate on dq s , dqs , dm bus - 4n prefetch architectu re ? t hroughput of valid commands - posted cas and additive latency (al) ? signal integrity - configurable ds for system compatibility - configurable on - die termination ? data integrity - auto refresh and self refresh modes ? power saving modes - power down mode ? sstl_18 compliance and power supply - vdd /vddq = 1.70 to 1.9 0 v density / packages information lead - free rohs compliance and halogen - fre e 512mb ( org. / package) width x length (mm) ball pitch (mm) 64 mb x 8 60 v f bga 8 .00 x 10 .00 0.8 0 32 mb x 16 84 v f bga 8 .00 x 12.5 0 0.8 0 density and addressing configuration 64 mb x 8 32 mb x 16 number of bank s 4 4 bank address ba0 C ba 1 ba0 C ba 1 auto precharge a10/ap a10/ap row address a0 - a1 3 a0 - a12 column address a0 - a9 a0 C a 9 page size 1 kb 2 kb features options ? temperature range ( tc ) 2 - commercial grade = 0 ~ 95 - quasi industrial grade ( - t ) = - 2 0 ~ 9 5 - industrial grade ( - i ) = - 40 ~ 9 5 - automotive grade 2 ( - h ) = - 40 ~ 10 5 - automotive grade 3 ( - a ) = - 40 ~ 9 5 notes: 1. for high speed bin backward compatible support, please refer to speed and voltage compatibility table. 2. if t c exceeds 85c, the dram must be refreshed externally at 2x refresh . i t is required to set tr e fi=3.9s in auto refresh mode and to set 1 for emrs (2) bit a7 in self refresh mode . ? output drive impedance ( full, reduced) ? burst length (4 , 8) ? burst t ype (sequential , interleave d ) ? rtt (50, 75, 150) programmable functions ? cas l atency ( 3 , 4 , 5 , 6 , 7 ) ? additive latency (0, 1, 2, 3, 4, 5, 6) ? wr (2, 3, 4, 5, 6, 7, 8) ? speed grade ( datarate/cl - trcd - trp) 1 - 1066 mbps / 7 - 7 - 7 - 800 mbps / 5 - 5 - 5 nanya technology corp. nt5tu 64 m8 e e / n t5tu 32 m16 e g
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 2 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved ordering information lead - free rohs compliance and halogen - fre e notes 1. please confirm with ntc for the available schedule. commercial grade organization part number package speed data rate(mbps) cl - t rcd - t rp 64 mb x 8 nt5 tu 64 m8 e e - ac 60 - ball 800 5 - 5 - 5 32 mb x 16 nt5tu 32 m16 e g - be 84 - ball 1066 7 - 7 - 7 nt5tu 32 m16 e g - ac 800 5 - 5 - 5 industrial grade organization part number package speed data rate(mbps) cl - t rcd - t rp 64 mb x 8 nt5tu 64 m8 e e - aci 60 - ball 800 5 - 5 - 5 32 mb x 16 nt 5tu 32 m16 e g - aci 84 - ball 800 5 - 5 - 5 quasi industrial grade 1 organization part number package speed data rate(mbps) data rate(mbps) 64 mb x 8 nt5tu 64 m8 e e - ac t 60 - ball 800 5 - 5 - 5 32 mb x 16 nt5tu 32 m16 e g - ac t 84 - ball 800 5 - 5 - 5 automotive grade 1 organizat ion part number package speed data rate(mbps) cl - t rcd - t rp 32 mb x 16 nt5tu 32 m16 e g - aca 84 - ball 800 5 - 5 - 5 nt5tu 32 m16 e g - ach
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 3 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved speed and voltage compatibility part number / speed & voltag e compatibility data rate mbps 1066 800 800 667 vdd v 1. 8 1. 8 1. 8 1. 8 cl - trcd - trp tck 7 - 7 - 7 6 - 6 - 6 5 - 5 - 5 5 - 5 - 5 nt5tu32m16eg - be o o o o nt5tu64m8ee - ac x o o o nt5tu32m16eg - ac x o o o nt5tu 64 m8 e e - aci x o o o nt5tu 32 m16 e g - aci x o o o nt5tu 64 m8 e e - act x o o o nt5tu 32 m16 e g - act x o o o nt5tu 32 m16 e g - aca x o o o nt5tu 32 m16 e g - ach x o o o note1 o : support ; x : unsupported note2 regarding the special operating frequency which is within the highest and the lowest speed frequencies but not declar ed here, please choose drams loose specification and condition from its neighboring defined frequencies.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 4 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved major timing specifications ddr2 - 1066, ddr2 - 800 and ddr2 - 667 speed bin ddr2 - 1066 ddr2 - 800 ddr2 - 667 units cl - trcd - trp 7 - 7 - 7 5 - 5 - 5 6 - 6 - 6 5 - 5 - 5 parameter min m ax min max m in max min max trcd 13.125 - 12.5 - 15 - 15 - ns trp 13.125 - 12.5 - 15 - 15 - ns trc 58.125 - 57.5 - 60 - 60 - ns tras 45 70k 45 70k 45 70k 45 70k ns tck(avg) , cl=5 2.5 7.5 2.5 8 3 8 3 8 ns tck(avg) , cl=6 2.5 7.5 2.5 8 2.5 8 option 1 ns tck(avg) , cl=7 1.875 7.5 option 1 option 1 ns notes 1. please confirm with ntc for its availability.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 5 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved n t n a n y a t e c h n o l o g y p r o d u c t f a m i l y 5 t = d d r 2 s d r a m u 6 4 m 8 e e a c n a n y a c o m p o n e n t p a r t n u m b e r i n g g u i d e o r g a n i z a t i o n ( d e p t h , w i d t h ) 3 2 m 1 6 = 6 4 m 8 = 5 1 2 m b n o t e : m = m o n o d e v i c e v e r s i o n e = 5 t h v e r s i o n s p e e d a c = d d r 2 - 8 0 0 5 - 5 - 5 b e = d d r 2 - 1 0 6 6 7 - 7 - 7 s p e c i a l t y p e o p t i o n p a c k a g e c o d e r o h s + h a l o g e n f r e e e = 6 0 - b a l l v f b g a g = 8 4 - i n t e r f a c e & p o w e r ( v d d & v d d q ) u = s s t l _ 1 8 ( 1 . 8 v , 1 . 8 v ) n a = c o m m e r c i a l g r a d e i = i n d u s t r i a l g r a d e h = a u t o m o t i v e g r a d e 2 a = a u t o m o t i v e g r a d e 3 t = q u a s i i n d u s t r i a l g r a d e 5 t b a l l v f b g a
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 6 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved 60 - ball vf bga ballout and package outline drawing (x 8 ) < top view> see the balls through the package unit: mm * bsc ( b asic s pacing between c enter ) 1 2 3 4 5 6 7 8 9 a vdd nu, rdqs vss vssq dqs vddq a b dq6 vssq dm,rdqs dqs vssq dq7 b c vddq dq1 vddq vddq dq0 vddq c d dq4 vssq dq3 dq2 vssq dq5 d e vddl vref vss vssdl ck vdd e f cke we ras ck odt f g nc ba0 ba1 cas cs g h a10/ap a1 a2 a0 vdd h j vss a3 a5 a6 a4 j k a7 a9 a11 a8 vss k l vdd a12 nc nc a13 l 1 2 3 4 5 6 7 8 9
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 7 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved 84 - ball vf bga ballout and package outline drawing (x 16 ) < top view> see the balls through the package unit: mm * bsc ( b asic s pacing between c enter ) 1 2 3 4 5 6 7 8 9 a vdd nc vss vssq udqs vddq a b dq14 vssq udm udqs vssq dq15 b c vddq dq9 vddq vddq dq8 vddq c d dq12 vssq dq11 dq10 vssq dq13 d e vdd nc vss vssq ldqs vddq e f dq6 vssq ldm ldqs vssq dq7 f g vddq dq1 vddq vddq dq0 vddq g h dq4 vssq dq3 dq2 vssq dq5 h j vddl vref vss vssdl ck vdd j k cke we ras ck odt k l nc ba0 ba1 cas cs l m a10/ap a1 a2 a0 vdd m n vss a3 a5 a6 a4 n p a7 a9 a11 a8 vss p r vdd a12 nc nc nc r 1 2 3 4 5 6 7 8 9
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 8 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved ball description s symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck an d ck (both directions o f crossing). cke input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power - down and self - refresh operation (all banks idle), or active power - down (row active in any bank). cke is synchronous for power down entry and exit and for self - refresh entry. cke is asynchronous for self - refresh exit. after v ref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self - refresh entry and exit, v ref must maintain to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power down. inp ut buffers, excluding cke, are disabled during self - refresh. cs input chip select: all command s are masked when cs is registered high. cs provides for external rank selection on systems with multiple memory ranks. cs is considered part of the command code . ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm ( ldm, udm ) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ba0 C ba 1 input bank address inputs: ba0 and ba 1 define to which bank an active, read, write or precharge comm and is being applied. bank address also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. a0 C a1 3 input address inputs: provides the row address for activate commands and the column address and auto p recharge or read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the p recharge applies to one bank (a10=low) or all banks (a10=high). if only one bank is t o be precharged, the bank is selected by ba0 - ba 1 . the address inputs also provide the op - code during mode register set commands. dq input/output data inputs/output: bi - directional data bus.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 9 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved symbol type function dqs, ( dqs ) (udqs), ( udqs ) (ldqs), ( ldqs ) input/output data strobe: output with read data, input with write data. edge aligned with read data, centered with write data. for the x16, ldqs corresponds to the data on dq0 - dq7; udqs corresponds to the data on dq8 - d q15. the data strobes dqs, ldqs and udqs may be used in single ended mode or paired with the optional complementary signals dqs , ldqs and udqs to provide differential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or disables the complementary data strobe signals. odt input on die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. for x16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal. the odt pin will be ignored if the emrs (1) is programmed to disable odt. nc - no connect: no internal electrical connection is present. v ddq supply dq power supply: 1.8v 0.1v v ssq supply dq ground v ddl supply dll power supply: 1.8v 0.1v v ssdl su pply dll ground v dd supply power supply: 1.8v 0.1v v ss supply ground v ref supply sstl_1.8 reference voltage note 1: the signal may show up in a different symbol but it indicates the same thing. e.g., /ck = ck# = ck? = ckb, /dqs = dqs# = dqs? = dqsb, /cs= cs# = cs? = csb.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 10 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved functional description s the 512 mb ddr2 sdram is a high - speed cmos, dynamic random - access mem ory containing 536 , 870 , 912 bits . read and write accesses to the ddr2 sdram are burst oriented; accesses s tart at a selected location and continue for the burst length of four or eight in a programmed sequence. accesses begin with the registration of an activate command, which is followed by a read or write command. the address bits registered coincident with the activate command are used to select the ba nk and row to be accesses (ba0 - ba 1 select the bank, a0 - a1 3 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst ac cess and to determine if the auto - precharge command is to be issued. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptio n and device operation.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 11 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved power - up and initialization ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the following sequence is required for power up and initialization. 1. either one of the following sequence is required for power - up. (1) while applying power, attempt to maintain cke below 0.2 x vddq and odt at a low state (all other inputs may be unde fined) the vdd voltage ramp time must be no gre ater than 200ms from when vdd ramps from 300mv to vdd min; and during the vdd voltage ramp up, ivdd - vddqi Q 0.3 volts. once the ramping of the supply voltages is complete (when vddq crosses vddq min), the supply voltage specifications in re - commanded dc operating conditions table. - vdd , vddl , and vddq are driven from a signal power converter output, and - vtt is limited to 0.95v max, and - vref tracks vddq/ 2; vref must be within 300mv with respect to vddq/2 during supply ramp time. - vddq>=vref must be met at all times. (2) while applying power, attempt to maintain cke below 0.2 x vddq and odt at a low state, all other inputs may be unde fined, voltage levels at i/os and outputs must be less than vddq during voltage ramp time to avoid dram latch - up. during the ramping of the supply voltages, vdd R vddl R vddq must be maintained and is applicable to both ac and dc levels until the ramping of the supply voltages is complete, which is when vddq crosses vddq min. once the ramping of the supply voltages is complete, the supply voltage specifications provi ded in re - commanded dc operating conditions table. - apply vdd/vddl before or at the same time as vddq. - vdd/vddl voltage ramp time must be no greater than 200ms from when vdd ramps from 300mv to vddmin. - apply vddq before or at the same time as vtt. - t he vddq voltage ramp time from when vdd min is achieved on vdd to when vddq min is achieved on vddq must be no greater than 500ms. (note: while vdd is ramping, current may be supplied from vdd through the dram to vddq. ) - vref must track vddq/ 2; vref must be within 300mv with respect to vddq/2 during supply ramp time. - vddq R vref must be met at all time. - apply vtt. 2. start clock ( ck, ck ) and maintain stable condition.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 12 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved 3. for the minimum of 200us after stable power (vdd, vddl, vddq, vref, and vtt are between their minimum and maximum values as stated in re - commanded dc operating conditions table, and stable clock, then apply nop or deselect & take cke high. 4. wait minimum of 400 ns then issue precharge all command. nop or deselect applied during 400 n s period. 5. issue an emrs command to emr(2). (to issue emrs command to emr(2), provide low to ba0 and ba 1 ,high to ba1.) 6. issue an emrs command to emr(3). (to issue emrs command to emr(3), provide low to ba 1 , high to ba0 and ba1.) 7. issue emrs to enable dll. (to issue dll enable command, provide low to a0, high to ba0 and low to ba1 - ba 1 and a1 2 - a13 . and a9=a8=a7=low must be used when issuing this command.) 8. issue a mode register set command for dll reset.(to issue dll reset command, provide high to a8 and low to ba0 - ba 1 .) 9. issue a precharge all command. 10. issue 2 more auto - refresh commands. 11. issue a mrs command with low to a8 to initialize device operation (i.e. to program operating parameters without resetting the dll.) 12. at least 200 clocks a fter step 7, execute ocd calibration (off chip driver impedance adjustment). if ocd calibration is not used, emrs to emr ( 1) to set ocd calibration default (a9=a8=a7=high) followed by emrs to emr ( 1) to exit ocd calibration mode (a9=a8=a7=low) must be issu ed with other operating parameters of emr(1). 13. the ddr2 dram is now ready for normal operation. * to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. example : ck , ck 1 st auto refresh mrs pre all emrs cmd 2 nd auto refresh trp trp trfc trfc extended mode register set with dll enable mode register set with dll reset pre all tmr d tmr d min . 200 cycles to lock the dll cke command 400 ns mrs nop tmr d emrs follow ocd flowchart odt " low " follow ocd flowchart emrs
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 13 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved register definition progra mming the mode registration and extended mode registers for application flexibility, burst length, burst type, cas latency, dll reset function, write recovery time (twr) are user defined variables and must be programmed with a mode register set (mrs) comma nd. additionally, dll disable function, additive cas latency, driver impedance, odt (on die termination), single - ended strobe and ocd (off chip driver impedance adjustment) are also user defined variables and must be programmed with an extended mode regist er set (emrs) command. contents of the mode register (mr) and extended mode registers ( emr ( #)) can be altered by re - executing the mrs and emrs commands. if the user chooses to modify only a subset of the mrs or emrs variables, all variables must be redefi ned when the mrs or emrs commands are issued. mrs, emrs and dll reset do not affect array contents, which mean re - initialization including those can be executed any time after power - up without affecting array contents. mode registration set (mr s ) the mod e register stores the data for controlling the various operating modes of ddr2 sdram. it controls cas latency, burst length , burst sequence, test mode, dll reset, twr and various vendor specific options to make ddr2 sdram useful for various applications. t he default value of the mode register is not defined, therefore the mode register must be written after power - up for proper operation. the mode register is written by asserting low on cs , ras , cas , we , ba0 , ba1 and ba 1 , while controlling the state of address pins a0 ~ a1 3 . the ddr2 sdram should be in all banks precharged (idle) mode with cke already high prior to writing into the mode register. the mode register set command cycle time ( t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharged state. the mode registe r is divided into various fields depending on functionality. burst length is defined by a0 ~ a2 with options of 4 and 8 bit burst length. burst address sequence type is defined by a3 and cas latency is defined by a4 ~ a6. a7 is used for test mode and must be set to low for normal mrs operation. a8 is used for dll reset. a9 ~ a11 are used for write recovery time (wr) definition for auto - precharge mode.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 14 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved mode register C mr programming note 1 bi ts of r eserved for future use must be set to 0 when programming the mr. note 2 for ddr2 - 400/533, wr (write recovery for autoprecharge) min is determined by tck max and wr max is determined by tck min. wr in clock cycles is calculated by dividing twr (in ns ) by tck (in ns) and rounding up to the next integer (wr[cycles] = ru{ twr[ns] / tck[ns] }, where ru stands for round up). for ddr2 - 667/800 /1066 , wr min is determined by tck(avg) max and wr max is determined by tck(avg) min. wr[cycles] = ru{ twr[ns] / tck( avg)[ns] }, where ru stands for round up. the mode register must be programmed to this value. this is also used with trp to determine tdal. ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 ppd dll tm bt a12 a8 a3 0 0 0 1 1 1 ba1 ba0 a7 0 0 0 0 1 1 a2 a1 a0 bl 1 0 0 1 0 4 1 1 0 1 1 8 a11 a10 a9 a6 a5 a4 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 8 7 5 4 6 5 7 6 2 reserved 3 reserved 4 3 emrs(2) emrs(3) wr cas latency reserved reserved mr select mode mr normal emrs(1) test fast exit (txard) no sequential slow exit (txards) yes interleave mr select wr cas latency burst length ppd dll reset burst type ddr2 - 667 ddr2 - 800 ddr2 - 1066
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 15 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved extended mode register set - emrs (1) programming single - ended and differential data strobe signals a11 a10 strobe function matrix rdqs dqs rdqs/dm rdqs dqs dqs 0(disable) 0(enable) dm hi - z dqs dqs 0(disable) 1(disable) dm hi - z dqs hi - z 1(enable) 0(enable) rdqs rdqs dqs dqs 1(enable) 1(disable) rdqs hi - z dqs hi - z note 1 default must be set to 0. ocd calibration is unsupported. note 2 bits of r eserve d for future use must be set to 0 when programming the e mr (1) . note 3 output disabled - dqs, dqss, dqs? , rdqs, rdqs . this feature is used in conjunction with dimm idd measurements when iddq is not desired to be included. note 4 if rdqs is enabled, the dm function is disabled. rdqs is active for reads and dont care for writes. ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 qoff rdqs /dqs rtt_nom rtt_nom d.i.c dll ba1 ba0 a10 /dqs a0 0 0 0 enabled 0 0 1 1 disabled 1 1 0 1 1 a11 rdqs a6 a2 0 disabled 0 0 1 enabled 0 1 0 1 0 1 a12 1 1 0 1 a5 a4 a3 0 0 0 0 0 1 a9 a8 a7 0 1 0 0 0 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 mr select ocd cal al mr select dll enable mr enable emrs(1) disable emrs(2) emrs(3) rtt_nom a1 output driver impedance disabled 75 ohm full strength 150 ohm reduced strength qoff 50 ohm output buffer enabled output buffer disabled al 0 1 ocd cal 1 2 6 reserved default 3 4 5
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 16 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved extended mode register set C emrs (1) the extended mode register emrs( 1) stores the data for enabling or disabling the dll, output driver strength, additive latency, odt, dqs disable, ocd program, rqds enable. the default value of the extended mode register emrs(1) is not defined, therefore the extended mode register must be written after power - up for proper operation. the extended mode register is written by asserting low on cs , ras , cas , we , ba1 , and high on ba0, while controlling the state of the address pins. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register. the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the emrs ( 1). mode register contents can be changed using the same command and clock cycle requirem ents during normal operation as long as all banks are in precharge state. a0 is used for dll enable or disable. a1 is used for enabling a half strength output driver. a3 - a5 determines the additive latency, a7 - a9 are used for ocd control, a10 is used for dqs disable and a11 is used for rdqs enable. a2 and a6 are used for odt setting. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self - refresh operation and is automatically re - enabled and reset upon exit of self - refresh operation. any time the dll is reset, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. less clock cycles may result in a violation of the t ac or t dqsck parameters. output disable (qoff) under normal operation, the dram outputs are enabled during read operation f or driving data (q off bit in the emrs ( 1) is set to 0). when the q off bit is set to 1, the dram outputs will be disabled. disabling the dram outputs allows users to measure i dd currents during read operations, without including the output buffer current an d external load currents.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 17 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved extended mode register set - emrs (2) programming note 1 user can set the e mr(2) [a3] bit to enable dcc. note 2 default must be set to 0. pasr is unsupported. note 3 c ontroller has to set the emr(2)[a7] bit to enable the self - refresh rate in case of higher than 85 c temperature self - refresh operation. note 4 bits of r eserved fo r future use must be set to 0 when programming the e mr (2) . ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 srf dcc a7 a3 0 0 1 1 ba1 ba0 a2 a1 a0 0 0 0 0 0 0 1 1 0 1 1 pasr 2 mr select 0 0 pasr dcc 1 high temperature self-refresh rate 3 disable enable mr0 default emrs(1) emrs(2) emrs(3) disable enable mr select
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 18 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved extended mode register set emrs ( 2) the extended mode registers ( 2) controls refresh related features. the default value of the extended mode register(2) is not defined, therefo re the extended mode register(2) is written by asserting low on cs , ras , cas , we , ba0, high on ba1, while controlling the states of address pin a0 - a1 3 . the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register ( 2). the mode register set command cycle time (tmrd) must be satisfied to complete the write operation to the extended mode register ( 2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. extended mode register set - emrs (3) programming all bits in emrs(3) expect ba0 and ba1 are reserved for future use and must be programmed to 0 when setting the mode register during initializatio n. ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 0
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 19 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved on - die termination (odt) odt (on - die termination) is a feature that allows a dram to turn on/off termination resistance for each dq, dq, dqs, dqs , rdqs, rdqs , and dm signal for x16 configuration odt is applied to each dq, udqs, udqs , ldqs, ldqs , udm and ldm signal via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance for any or all dram devices. the odt function can be u sed for all active and standby modes. odt is turned off and not supported in self - refresh mode. functional representation of odt switch sw1, sw2, or sw3 is enabled by the odt pin. selection between sw1, sw2, or sw3 is determine d by rtt (nominal) in emrs. termination included on all dqs, dm, dqs, dqs , rdqs, and rdqs pins . dram input buffer input pin rval 1 rval 1 rval 2 rval 2 sw 1 sw 1 sw 2 sw 2 vddq vddq vssq vssq rval 3 rval 3 sw 3 sw 3 vddq vssq
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 20 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved odt related timings mrs command to odt update delay during normal operation the value of the effective termination resistance can be changed with an emrs com mand. the update of the rtt setting is done between tmod, min and tmod, max, and cke must remain high for the entire duration of tmod window for proper operation. the timings are shown in the following timing diagram. however, to prevent any impedance glitch on the channel, the following conditions must be met. - taofd must be met before issuing the emrs command. - odt must remain low for the entire duration of tmod window, until tmod, max is met. now the odt is ready for normal operation with the new setting, and the odt may be raised again to turn on the odt. following timing diagram shows the proper rtt update procedure. cke rtt ck , ck t is cmd taofd emrs nop nop nop nop nop tmod , min tmod , max old setting updating new setting emrs command directed to emr ( 1 ) , which updates the information in emr ( 1 )[ a 6 , a 2 ] , i . e . rtt ( nominal ) setting in this diagram is the register and i / o setting , not what is measured from outside . cke rtt ck , ck t is cmd taofd emrs nop nop nop nop tmod , max old setting new setting emrs command directed to emr ( 1 ) , which updates the information in emr ( 1 )[ a 6 , a 2 ] , i . e . rtt ( nominal ) setting in this diagram is the register and i / o setting , not what is measured from outside . taond nop
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 21 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved odt on/off timings odt timing for active/standby mode odt timing for power - down mode r t t t i s t i s t i s t a o n d t a o f d ( 2 . 5 t c k ) t - 3 t - 5 t - 4 t - 0 t - 2 t - 1 t - 6 c k e i n t e r n a l t e r m r e s . o d t c k , c k t a o n , m i n t a o n , m a x t a o f , m i n t a o f , m a x t i s t i s t a o f p d , m a x r t t t a o n p d , m i n t a o f p d , m i n t a o n p d , m a x t 5 t 6 t 4 t 3 t 2 t 0 t 1 c k e d q o d t c k , c k
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 22 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved bank activate command the bank activate command is issued by holding cas and we high plus cs and ras l ow at the rising edge of the clo ck. the bank addresses ba0 ~ ba 1 are used to select the desired bank. r ow addresses a0 through a1 3 have to be applied. the bank activate command must be applied before any read or write opera tion can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write comma nd (with or without auto - precharge) on the following clock cycle. if an r/w command is issued to a bank that has not satisfied the t rcdmin speci fication, then additive latency must be programmed into the device to delay the r/w command which is internally issued to the device. the additive latency value must be chosen to assure t rcdmin is satisfied. additive latencies of 0, 1, 2, 3, 4, 5, and 6 ar e supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between success ive bank activate commands to the same bank is determined (t rc ). the minimum time interval between bank active commands, to other bank, is the bank a to bank b delay time (t rrd ). in order to ensure that 8 bank devices do not exceed the instantaneous curren t supplying capability of 4 bank devices, certain restrictions on operation of the 8 bank devices must be observed. there are two rules. one for restricting the number of sequential act commands that can be issued and another for allowing more time for ras precharge for a precharge all command. the rules are list as follow: * 8 bank device sequential bank activation restriction: no more than 4 banks may be activated in a rolling tfaw window. conve r ting to clocks is done by dividing tfaw by tck and rounding up to next integer value. as an example of the rolling window, if (tfaw/tck) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued in clock n+1 through n+9. *8 bank device precharge all allowance: trp for a precharge all command for an 8 bank device will equal to trp+tck, where trp is the value for a single bank pre - charge. bank activate command cycle: t rcd = 3, al = 2, t rp = 3, t rrd = 2, t ccd = 2 address nop command t 0 t 2 t 1 t 3 t 4 col . addr . bank a row addr . bank b col . addr . bank b internal ras - cas delay trcdmin . bank a to bank b delay trrd . activate bank b read a posted cas activate bank a read b posted cas read a begins row addr . bank a addr . bank a precharge bank a nop addr . bank b precharge bank b row addr . bank a activate bank a trp row precharge time ( bank a ) trc row cycle time ( bank a ) tn tn + 1 tn + 2 tn + 3 act ras - ras delay trrd . tras row active time ( bank a ) additive latency al = 2 ck , ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 23 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved read an d write commands and access modes after a bank has been activated, a read or write cycle can be executed. this is accomplished by setting ras high, cs and cas low at the clocks rising edge. we must also be defined at this time to determine whether the acc ess cycle is a read operation ( we high) or a write operation ( we low). the ddr2 sdram provides a fast column access operation. a single read or write command will initiate a serial read or write operation on successive clock cycles. the boundary of the bur st cycle is restricted to specific segments of the page length. a new burst access must not interrupt the previous 4 bit burst operation in case of bl = 4 setting. however, in case of bl=8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary respectively , and t he minimum cas to cas delay (t ccd ) is minimum 2 clocks for read or write cycles. posted cas posted cas operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a read or write co mmand to be issued immediately after the ras bank activate com mand (or any time during the ras to cas delay time, t rcd , period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is the sum of al and the cas latency (cl). therefore if a user chooses to issue a read/write command before the trcdmin, then al greater than 0 must be written into the emrs ( 1). the write latency (wl) is always defined as rl - 1 (read latency - 1) where read latency is defined as the sum of additive latency plus cas latency (rl=al+cl). if a user chooses to issue a read command after the t rcdmin period, the read latency is also defined as rl = al + cl. example of posted cas dout 0 dout 1 dout 2 dout 3 cmd dq 0 2 3 4 5 6 7 8 9 10 11 12 - 1 1 > = trcd al = 2 rl = al + cl = 5 cl = 3 wl = rl - 1 = 4 din 0 din 1 din 2 din 3 postcas 1 dqs , dqs activate read write bank a bank a bank a ck , ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 24 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved read followed by a write to the same bank: al = 0, cl = 3, rl = (al + cl) = 3, wl = (rl - 1) = 2, bl = 4 activate bank a 0 2 3 4 5 6 7 8 9 10 11 12 - 1 1 cmd dq > = trcd rl = al + cl = 3 wl = rl C 1 = 2 postcas 5 dqs , dqs read bank a din 0 din 1 din 2 din 3 dout 0 dout 1 dout 2 dout 3 write bank a ck , ck al = 0 cl = 3
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 25 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst mode operation burst mode operat ion is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst type, either sequential or interleaved, is programmable and defined by the ad dress bit 3 (a3) of the mrs. seamless burst read or write operations are supported. interruption of a burst read or write operation is prohibited, when burst length = 4 is programmed. for burst interruption of a read or write burst when burst length = 8 is used, see the burst interruption section of this datasheet. a burst stop command is not supported on ddr2 sdram devices. bu r st length and sequence burst length starting address sequential addressing (decimal) interleave addressing (decimal) a2 a1 a0 4 - 0 0 0, 1, 2, 3 0, 1, 2, 3 - 0 1 1, 2, 3, 0 1, 0, 3, 2 - 1 0 2, 3, 0, 1 2, 3, 0, 1 - 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 26 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the delay from the start of the command until the data from the first cell appears on the outputs is equal to the value of the read latency (rl). the data strobe output (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data - out appears on the dq pin in phase with the dqs signal in a source synchronous manner. the rl is equal to an additive latency (al) plus cas latency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register set (emrs (1)) basic burst read timing examples: burst read operation: rl = 5 (al = 2, cl = 3, bl = 4) dqs, dqs dq dqs dqs t rpre t dqsqmax t rpst t dqsck t ac dout dout dout dout clk, clk clk clk t ch t cl t ck do-read t qh dqsqmax t qh t t lz t hz nop nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop <= t dqsck cmd dq bread523 dqs, dqs post cas ck, ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 27 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst read operation: rl = 3 (al = 0, cl = 3, bl = 8) burst read followed by burst write : rl = 5, wl = (rl - 1) = 4, bl = 4 the minimum time from the burst read command to the burst write command is defi ned by a read - to - write - turn - around time(trtw), which is 4 clocks in case of bl=4 operation, 6 clocks in case of bl=8 operation. cmd nop nop nop nop nop nop dq's nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 3 cl = 3 nop <= t dqsck bread303 dqs, dqs dout a4 dout a5 dout a6 dout a7 ck, ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 28 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved seamless burst read operation: rl = 5, al = 2, cl = 3, bl = 4 the seamle ss burst read operation s s upported by enabling a read command at every clock for bl=4 operation, and every 4 clock for bl =8 operation. this operation allow s regardless of same or different banks as long as the banks activated. burst write command the burst write command is initia ted by having cs , cas and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. write latency (wl) is defined by a read latency (rl) minus one and is equal to (al + cl - 1). a data strobe signal (dqs) has to be driven low (preamble) a time twpre prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the tdqss specification must be satisfied for write cycles. the subs equent burst bit data are issued on successive edges of the dqs until the burst length is completed, which is 4 or 8 bit burst. when the burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the bur st write operation is complete. the time from the completion of the burst write to bank precharge is named write recovery time (wr). ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the em rs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing measured is mode dependent. basic burst write timing nop nop nop nop nop nop nop read a post cas read b post cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 rl = 5 al = 2 cl = 3 sbr523 cmd dq dqs, dqs ck, ck dqs , dqs dqs dqs t dqsh t dqsl t wpre wpst t din din din din t ds t dh
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 29 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved example : burst write operatio n: rl = 5 ( al = 2, cl = 3), wl = 4, bl = 4 nop nop nop nop nop precharge nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 4 bw543 cmd dq nop din a0 din a1 din a2 din a3 <= t dqss twr completion of the burst write dqs, dqs ck, ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 30 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst read followed by burst write : rl = 5, wl = (rl - 1) = 4, bl = 4 the minimum time from the burst read command to the burst write command is defined by a read - to - write - turn - around time(trtw), which is 4 clocks in case of bl=4 operation, 6 clocks in case of bl=8 operation. burst write followed by burst read: rl = 5 ( al = 2, cl = 3), wl = 4, twtr = 2, bl = 4 the minimum number of clocks from the burst wri te command to the burst read command is (cl - 1) +bl/2 + t wtr where t wtr is the write - to - read turn - around time t wtr expressed in clock cycles. the t wtr is not a write recovery time (t wr ) but the time required to transfer 4 bit write data from the input buf fer into sense amplifiers in the array. seamless burst write operation: rl = 5, wl = 4, bl = 4 the seamless burst write operation is supported by enabling a write command every bl / 2 number of clocks. this operation is allowe d regardless of same or different banks as long as the banks are activated. nop nop nop nop nop read a post cas bwbr cmd dq nop din a0 din a1 din a2 din a3 al=2 cl=3 nop nop twtr t0 t2 t1 t3 t4 t5 t6 t7 t8 t9 write to read = (cl - 1)+ bl/2 +twtr(2) = 6 dqs, dqs wl = rl - 1 = 4 rl=5 ck, ck nop nop nop nop nop nop nop din a0 din a1 din a2 din a3 write a post cas wl = rl - 1 = 4 write b post cas din b0 din b1 din b2 din b3 t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq sbr dqs, dqs ck, ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 31 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved write data mask one write data mask input (dm) pin for each 8 data bits (dq) will be supported on ddr2 sd rams, consistent with the imple mentation on ddr sdrams. it has identical t imings on write operations as the data bits, and though used in a uni - directional manner, is internally loaded identically to data bits to insure matched system timing. dm of x16 bit organization is not used during read cycles. write data mask timing burst write operation with data mask: rl = 3 (al = 0, cl = 3), wl = 2, t wr = 3, bl = 4 dqs dqs , dqs dqs t dqsh t dqsl t wpre wpst t dq din din din din t ds dh t dm don ' t care nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = rl-1 = 2 dm cmd dq nop twr <= t dqss precharge bank a activate trp dqs, dqs dm din a0 din a1 din a3 din a2 ck, ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 32 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst interruption interruption of a read or write burst is only allowed on burst of 8. burst interrupt of 4 is p rohibited . below are the constraints of burst interruption: 1. a read burst of 8 can only be interrupted by another read command. read burst interruption by a write or precharge command is prohibited. 2. a write burst of 8 can only be interrupted by anot her write command. write burst interruption by a read or precharge command is prohibited. 3. read burst interrupt occur exactly two clocks after the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt occur exactly two clocks after the previous write command. any other read burst interrupt timings are prohibited. 3. read or write burst interruption is allowed to any bank inside the ddr2 sdram. 4. read or write burst with auto - precharge enabled is not allowed to be interrupted. 5. read burst interruption is allowed by a read with auto - precharge command. 6. write burst interruption is allowed by a write with auto - precharge command. notes: 1. all command timings are referenced to burst length set in the mode register. they are not referenced to the actual burst. for example, minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). minimum write to precharge timing is wl + bl/ 2 + twr , where twr starts with the rising clock after the un - interrupted burst end and not form the end of the actual burst end .
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 33 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved examples: read burst interrupt timing example: (cl = 3, al = 0, rl = 3, bl = 8) write burst interrupt timing example: (cl = 3, al = 0, wl = 2, bl = 8) nop nop nop nop nop nop read a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq rbi dqs, dqs read b nop dout a0 dout a1 dout a2 dout a3 dout b0 dout b1 dout b2 dout b3 dout b4 dout b5 dout b6 dout b7 nop ck, ck nop nop nop nop nop write a t0 t2 t1 t3 t4 t5 t6 t7 t8 cmd dq wbi dqs, dqs nop din a0 din a1 din a2 din a3 din b0 din b1 din b2 din b3 dout b4 din b5 din b6 din b7 nop write b ck, ck nop
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 34 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is triggered when cs , ras and we are low and cas is high at the rising edge of the clock. the pre - charge command can be used to precharge each bank independently or all banks simultaneously. three add ress bits a10, ba0, and ba1 are used to define which bank to precharge whe n the command is issued. bank selection for precharge by address bit a10 ba1 ba0 precharge bank(s) low low low bank 0 only low low high bank 1 only low high low bank 2 only low high high bank 3 only high don't care don't care a ll banks burst read op eration followed by a precharge minimum read to precharge command spacing to the same bank = al + bl/2 + max (rtp , 2 ) - 2 clocks. for the earliest possible precharge, the precharge command may be issued on the rising edge which is additive latency (al) + bl/2 clocks after a read command, as long as the minimum tr as timing is satisfied. the minimum read to precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4 - bit prefetch of a read to precharge c ommand. this time is call trtp ( r ead t o p recharge). for bl=4 this is the time from the actual read (al after the read command) to precharge command. for bl=8 this is the time from al + 2 clocks after the read to the precharge command.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 35 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved examples: burst rea d operation followed by precharge: rl = 4 (al = 1, cl = 3), bl = 4, t rtp Q burst read operation followed by precharge: rl = 4 (al = 1, cl = 3), bl = 8, t rtp Q nop precharge nop bank a activate nop nop read a post cas t 0 t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 cmd dq br - p 413 nop al + bl / 2 clks dout a 0 dout a 1 dout a 2 dout a 3 al = 1 cl = 3 rl = 4 > = tras cl = 3 > = trp dqs , dqs nop > = trc > = trtp ck , ck nop nop nop post cas read a t 0 t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 cmd dq br - p 413 ( 8 ) nop al + bl / 2 clks dout a 0 dout a 1 dout a 2 dout a 3 al = 1 cl = 3 rl = 4 > = tras cl = 3 dqs , dqs nop > = trc > = trtp dout a 4 dout a 5 dout a 6 dout a 7 precharge nop nop first 4 - bit prefetch second 4 - bit prefetch ck , ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 36 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst read operation followed by precharge: rl = 5 (al = 2, cl = 3), bl = 4, t rtp Q burst read operation followed by precharge: rl = 6, (al = 2, cl = 4), bl = 4, t rtp Q nop nop nop bank a activate nop nop post cas read a t 0 t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 cmd dq br - p 523 nop al + bl / 2 clks dout a 0 dout a 1 dout a 2 dout a 3 al = 2 cl = 3 rl = 5 > = tras cl = 3 > = trp precharge dqs , dqs > = trc > = trtp ck , ck nop nop nop read a post cas t 0 t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 cmd dq br - p 624 nop al + bl / 2 clocks dout a 0 dout a 1 dout a 2 dout a 3 al = 2 cl = 4 rl = 6 > = tras cl = 4 precharge a bank a activate dqs , dqs nop nop > = trc > = trtp ck , ck > = trp
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 37 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst read operation followed by precharge: rl = 4, (al = 0, cl = 4), bl = 8, t rtp > 2 clocks burst write followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 + t wr . for write cycles, a delay must be satisfied from t he completion of the last burst write cycle until the precharge command can be issued. this delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prio r to the t wr delay, as ddr2 sdram does not support any burst interrupt by a precharge command. t wr is an analog timing parameter (see the ac table in this datasheet) and is not the programmed value for t wr in the mrs. examples: burst write followed by prec harge : wl = (rl - 1) = 3, bl = 4, t wr = 3 nop nop nop read a t 0 t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 cmd dq br - p 404 ( 8 ) nop al + bl / 2 clks + 1 dout a 0 dout a 1 dout a 2 dout a 3 cl = 4 rl = 4 > = tras > = trp dqs , dqs nop > = trtp dout a 4 dout a 5 dout a 6 dout a 7 precharge nop bank a activate first 4 - bit prefetch second 4 - bit prefetch ck , ck nop nop nop nop nop write a post cas t 0 t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 wl = 3 bw - p 3 cmd dq nop din a 0 din a 1 din a 2 din a 3 > = twr completion of the burst write precharge a nop dqs , dqs ck , ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 38 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst write followed by precharge : wl = (rl - 1) = 4, bl = 4, t wr = 3 nop nop nop nop nop write a post cas t0 t2 t1 t3 t4 t5 t6 t7 t9 wl = 4 bw-p4 cmd dq nop din a0 din a1 din a2 din a3 twr completion of the burst write precharge a nop dqs, dqs ck, ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 39 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved auto - precharge operation before a new row in an active bank can be opened, the act ive bank must be precharged using either the pre - charge command or the auto - precharge function. when a read or a write command is given to the ddr2 sdram, the cas timing accepts one extra address, column address a10, to allow the active bank to automatical ly begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burs t sequence. if a10 is high when the read or write command is issued, then the auto - precharge function is enabled. during auto - precharge, a read command will exe cute as normal with the exception that the active bank will begin to precharge internally on th e rising edge which is cas latency (cl) clock cycles before the end of the read burst. auto - precharge is also implemented for write commands. the precharge operation engaged by the auto - precharge command will not begin until the last data of the write burs t sequence is properly stored in the memory array. this feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas latency) thus improving system performance for random data access. the ras lock out circuit internally delays the precharge operation until the array restore operation has been completed so that the auto - precharge command may be issued with any read or write command . burst read with auto - precharge if a10 is high when a read command i s issued, the read with auto - precharge function is engaged. the ddr2 sdram starts an auto - precharge operation on the rising edge which is (al + bl/2) cycles later from the read with ap command if t ras (min) and t rtp are satisfied. if t ras (min) is not satisf ied at the edge, the start point of auto - precharge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the start point of auto - precharge operation will be delayed until t rtp (min) is satisfied. in case the int ernal precharge is pushed out by t rtp , t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with auto - precharge to the next activate command becomes al + t rtp + t rp . for bl = 8 the time from read with auto - precharge to the next activate command is al + 2 + t rtp + t rp . note that both parameters t rtp and t rp have to be rounded up to the next integer value. in any event internal pre charge does not start earl ier than two clocks after the last 4 - bit prefetc h. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously: (1) the ras precharge time (t rp ) has been satisfied from the clock at which the auto - precharge begins. (2) the ras cycle time (t rc ) from the previous bank activation has been satisfied.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 40 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved examples: burst read with auto - precharge followed by an activation to the sam e bank (t rc limit) rl = 5 (al = 2, cl = 3), bl = 4, t rtp Q burst read with auto - precharge followed by an activation to the same bank (tras limit): rl = 5 (al = 2, cl = 3), bl = 4, trtp Q nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5231 a10 ="high" trp auto-precharge begins dqs, dqs tras trcmin. nop al + bl/2 ck, ck nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 5 al = 2 cl = 3 nop cmd dq br-ap5232 a10 ="high" trp auto-precharge begins dqs, dqs trc tras(min) nop ck, ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 41 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst read with auto - precharge followed by an activation to the same bank: rl = 4 ( al = 1, cl = 3), bl = 8, t rtp Q burst read with auto - precharge followed by an activation to the same bank: rl = 4 ( al = 1, cl = 3), bl = 4, t rtp > 2 clocks nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap413(8)2 a10 ="high" trp auto-precharge begins dqs, dqs nop dout a4 dout a5 dout a6 dout a7 first 4-bit prefetch second 4-bit prefetch >= trtp al + bl/2 ck, ck nop nop nop nop bank activate nop read w/ap posted cas t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 al = 1 cl = 3 nop cmd dq br-ap4133 a10 ="high" auto-precharge begins dqs, dqs nop first 4-bit prefetch trtp al + trtp + trp trp ck, ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 42 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved burst write with auto - precharge if a10 is high when a write command is issued, the write with auto - precharge function is engaged. the ddr2 sdram automatically begins precharge operation after t he completion of the write burst plus the write recovery time delay (wr), programmed in the mrs register, as long as t ras is satisfied. the bank undergoing auto - precharge from the completion of the write burst may be reactivated if the following two condit ions are satisfied. (1) the last data - in to bank activate delay time (t dal = wr + t rp ) has been satisfied. (2) the ras cycle time (t rc ) from the previous bank activation has been satisfied. examples: burst write with auto - precharge (t rc limit ): wl = 2, t d al = 6 (wr = 3, t rp = 3 ), bl = 4 burst write with auto - precharge (t wr + t rp limit) : wl = 4, t dal = 6 (t wr = 3, t rp = 3), bl = 4 nop nop nop nop nop bank a activate nop write w/ap t0 t2 t1 t3 t4 t5 t6 t7 nop cmd dq bw-ap223 a10 ="high" trp auto-precharge begins din a0 din a1 din a2 din a3 wl = rl-1 = 2 wr trcmin. dqs, dqs completion of the burst write tdal >=trasmin. ck, ck nop nop nop nop nop bank a activate nop posted cas write w / ap t 0 t 3 t 4 t 5 t 6 t 7 t 12 nop cmd dq bw - ap 423 a 10 =" high " trp auto - precharge begins din a 0 din a 1 din a 2 din a 3 wl = rl - 1 = 4 twr > = trc t 9 t 8 completion of the burst write dqs , dqs tdal > = tras ck , ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 43 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved precharge & a uto p recharge c larification from command to command mi nimum delay between "from command" to "to command" units note read precharge (to same bank as read) al + bl/2 + max(rtp,2) - 2 tck 1,2 precharge all al + bl/2 + max(rtp,2) - 2 tck 1,2 read w/ap precharge ( to same bank as read w / ap) al + bl/2 + max(rtp ,2) - 2 tck 1,2 precharge al l al + bl/2 + max(rtp,2) - 2 tck 1,2 write precharge (to same bank as write) wl + bl/2 + twr tck 2 precharge al l wl + bl/2 + twr tck 2 write w/ap precharge (to same bank as write w/ap) wl + bl/2 + wr tck 2 precharge al l wl + bl/2 + wr tck 2 precharge precharge (to same bank as precharge) 1 tck 2 precharge al l 1 tck 2 precharge all precharge 1 tck 2 precharge al l 1 tck 2 note: 1) rtp [ cycles] = ru { trtp(ns)/tck(ns)}, where ri stands for round up. 2) for a given ban k, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. the precharge period is satisfied after trp or trpa depending on the latest precharge com mand issued to that ban k.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 44 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved refresh sdrams require a refresh of all rows in any rolling 64 ms interval. each refresh is generated in one of two ways: by an explicit auto - refresh command, or by an internally timed event in self - refresh mode. dividin g the number of device rows in to the roll ing 64 ms interval defined the average refresh interval t refi , which is a guideline to control for distributed refresh timing. auto - refresh command auto - refresh is used during normal operation of the ddr2 sdrams. this command is non persisten t, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits dont care during an auto - refresh command. the ddr2 sdram requires auto - refresh cycles at an aver age periodic inter val of t refi (maximum). when cs , ras and cas are held low and we high at the rising edge of the clock, the chip enters the auto - refresh mode. all banks of the sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the auto - refresh com mand can be applied. a n internal address counter supplies the addresses during the refresh cycle. no control of the external address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state . a delay between the auto - refresh command and the next activate command or subsequent auto - refresh command must be greater than or equal to the auto - refresh cycle time (t rfc ). to allow for improved efficiency in scheduling and switching between tasks, s ome flexibility in the absolute refresh interval is provided. a maximum of eight auto - refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any auto - refresh command and the next auto - refresh command is 9 * t refi . t0 t2 t1 t3 ar ck, ck cmd precharge > = t rp nop auto refresh any nop > = t rfc > = t rfc auto refresh nop nop nop cke "high"
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 45 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved self - refresh command the self - refresh command can be used to retain data, even if the rest of the system is powered down. when in the self - refresh mode, the ddr2 sdram retains data without external clocking. the dd r2 sdram device has a built - in timer to accommodate self - refresh operation. the self - refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. odt must be turned off before issuing self refresh command , by either driving odt pin low or using emrs ( 1) command. once the command is registered, cke must be held low to keep the device in self - refresh mode. when the ddr2 sdram has entered self - refresh mode all of the exter nal control signals, except cke, are disabled. the clock is internally disabled during self - refresh operation to save power. the user may change the external clock frequency or halt the external clock one clock after self - refresh entry is registered, how ever, the clock must be restarted and stable before the device can exit self - refresh operation. once self - refresh exit com mand is registered, a delay equal or longer than the t xsnr or t xsrd must be satisfied before a valid command can be issued to the device. cke must remain high for the ent ire self - refresh exit period (t xsnr or t xsrd ) for proper operation. nop or dese lect commands must be registered on each positive clock edge during the self - refresh exit interval. since the odt function is not supported during self - refresh operation, odt h as to be turned off t aofd before entering self - refresh mode and can be turned on again when the t xsrd timing is satisfied. ck/ck t1 t3 t2 ck/ck may be halted ck/ck must be stable cke >=txsrd >= txsnr t n t r t m t5 t4 trp* tis taofd cmd self refresh entry nop non-read command read command t0 tis tis odt * device must be in theing "all banks idle" state to enter self refresh mode. * odt must be turned off prior to entering self refresh mode. * txsrd (>=200 tck) has to be satisfied for a read or as read with auto-precharge commend. * txsnr has to be satisfied for any command execept read or a read with auto-precharge command, where txsnr is defined as trfc + 10ns. * the minium cke low time is defined by the t ckemin. timming paramester. * since cke is an sstl input, v ref must maintained during self-refresh.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 46 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved power - down power - down is synchronously entered when cke is registered low, along with nop or deselec t command. cke is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. cke is allowed to go low while any other operation such as row activation, precharge, auto - precharge or auto - refr esh is in progress, but power - down idd specification will not be applied until finishing those operations. the dll should be in a locked state when power - down is entered. otherwise dll should be reset after exiting power - down mode for proper read operation . if power - down occurs when all banks are precharged, this mode is referred to as precharge power - down ; if power - down occurs when there is a row active in any bank, this mode is referred to as active power - down . for active power - down two different power sa ving modes can be selected within the mrs register, address bit a12. when a12 is set to low this mode is referred as standard active power - down mode and a fast power - down exit timing defined by the t xard timing parameter can be used. when a12 is set to high this mode is referred as a power saving low power active power - down mode. this mode takes longer to exit from the power - down mode and the t xards timing parameter has to be satisfied. entering power - down deactivates the input and output buffers, excluding ck, ck, odt and cke. also the dll is disabled upon entering precharge power - down or slow exit active power - down, but the dll is kept enabled during fast exit active power - down. in power - down mode, cke low and a stable clock signal must be mainta ined at the inputs of the ddr2 sdram, and all other input signals are dont care. power - down duration is limited by 9 times trefi of the device. the power - down state is synchronously exited when cke is registered high (along with a nop or deselect comman d). a valid, executable command can be applied with power - down exit latency, t xp , t xard or t xards , after cke goes high. power - down exit latencies are defined in the ac spec table of this data sheet. power - down entry active power - down mode can be entered a fter an activate command. precharge power - down mode can be entered after a pre charge, precharge - all or internal precharge command. it is also allowed to enter power - mode after an auto - refresh command or mrs / emrs(1) command when t mrd is satisfied. active power - down mode entry is prohibited as long as a read burst is in progress, meaning cke should be kept high until the burst operation is finished. therefore active power - down mode entry after a read or read with auto - precharge command is allowed after rl + bl/2 is satisfied. active power - down mode entry is prohibited as long as a write burst and the internal write recovery is in progress. in case of a write command, active po wer - down mode entry is allowed t hen wl + bl/2 + twtr is satisfied. in case of a write command with auto - precharge, power - down mode entry is allowed after the internal precharge command has been executed, which wl + bl/2 + wr is starting from the write with auto - precharge command. in case the ddr2 sdram enters the precharge power - down mode .
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 47 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved examples: active power - down mode entry and exit after an activate command active power - down mode entry and exit after a read burst: rl = 4 (al = 1, cl =3), bl = 4 nop nop activate t0 t2 t1 cmd nop tn tn+1 cke active power-down entry nop nop act.pd 0 tis tn+2 tis active power-down exit valid command txard or txards *) ck, ck nop nop read t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a0 dout a1 dout a2 dout a3 rl = 4 cl = 3 cmd dq dqs, dqs nop nop nop nop nop nop tn tn+1 cke al = 1 active power-down entry rl + bl/2 nop nop act.pd 1 tis tn+2 tis active power-down exit valid command txard or txards *) ck, ck read w/ap
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 48 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved active power - down mode en try and exit after a write burst: wl = 2, twtr = 2, bl = 4 precharge power down mode entry and exit nop nop write t 0 t 2 t 1 t 3 t 4 t 5 t 6 t 7 cmd dq dqs , dqs nop nop nop nop nop nop tn tn + 1 cke wl = rl - 1 = 2 active power - down entry wl + bl / 2 + twtr nop nop act . pd 2 twtr tis tn + 2 tis valid command active power - down exit txard or txards *) ck , ck din a 0 din a 1 din a 2 din a 3 txp nop nop precharge *) t0 t2 t1 cmd nop nop tn tn+1 cke precharge power-down entry nop nop prepd tis tn+2 tis precharge power-down exit valid command trp nop t3 *) "precharge" may be an external command or an internal precharge following write with ap. ck, ck
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 49 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved no operation command the no operation command should be used in cases when the sdram is in a id le or a wait state. the purpose of the no oper ation command is to prevent the sdram from registering any unwanted commands between operations. a no operation com mand is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become dont care. input clock frequency change during operation the dram input clock frequency can be changed under the following condition s: a) during self - refresh operation b) dram is in precharge power - down mode and odt is completely turned off. the ddr2 - sdram has to be in precharged power - down mode and idle. od t must be already turned off and cke must be at a logic low state. after a mi nimum of two clock cycles after trp and taofd have been satisfied the input clock frequency can be changed. a stable new clock frequency has to be provided, before cke can b e changed to a high logic level again. after t xp has been satisfied a dll reset c ommand via emrs(1) has to be issued. during the following dll re - lock period of 200 clock cycles, odt must remain off. after the dll - re - lock period the dram is ready to operate with the new clock frequency. example: input frequency change during precharge power - down mode nop nop t0 t2 t1 t3 t4 tx tx+1 ty cmd nop nop nop nop nop dll reset ty+2 ty+3 cke frequency change occurs here nop nop frequ.ch. tz txp stable new clock before power-down exit ck, ck trp taofd minimum 2 clocks required before changing the frequency ty+1 nop valid command 200 clocks odt is off during dll reset
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 50 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved asynchronous cke low event dram requires cke to be maintained high for all valid operations as defined in this data sheet. if cke asynchronously drops low during any valid operation dram is not guaranteed to preserve the contents of the memory array. if this event occurs, the memory controller must satisfy a time delay ( t delay ) before turning off the clocks. stable clocks must exist at the input of dram before cke is raised high again. the dram must be fully re - initialized as described the the initialization sequence . dram is ready for normal operation after the initialization sequence. see ac timing parametric table for t delay specification. asynchronous cke low event c k e c k e d r o p s l o w d u e t o a n a s y n c h r o n o u s r e s e t e v e n t c l o c k s c a n b e t u r n e d o f f a f t e r t h i s p o i n t t d e l a y c k , c k s t a b l e c l o c k s
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 51 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved comm and truth table function cke cs ? ras ? cas ? we ? ba0 - ba 1 a11 - a1 3 a10 a 0 - a 9 notes previous cycle current cycle (extended) mode register set h h l l l l ba op code 1, 2 auto - refresh h h l l l h x x x x 1 self - refresh entry h l l l l h x x x x 1,8 self - refresh exit l h h x x x x x x x 1,7,8 l h h h single bank precharge h h l l h l ba x l x 1,2 precharge all banks h h l l h l x x h x 1 bank activate h h l l h h ba row address 1,2 write h h l h l l ba column l column 1,2,3 write with auto - precharge h h l h l l ba column h column 1,2,3 read h h l h l h ba column l column 1,2,3 read with auto - precharge h h l h l h ba column h column 1,2,3 no operation h x l h h h x x x x 1 device deselect h x h x x x x x x x 1 power down entry h l h x x x x x x x 1,4 l h h h power down exit l h h x x x x x x x 1,4 l h h h notes: 1. all ddr2 sdram commands are defined by states of cs , we , ras , cas , and cke at the rising edge of the clock. 2. bank addresses (bax) determine which bank is to be operated upon. for (e) mrs bax selects an (extended) mode register. 3. burst reads or writes at bl = 4 cannot be terminated. 4. the power down mode does not perform any refresh operations. the duration of power down is therefore limited by the refresh re quirements outlined. 5. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 6. x means "h or l (but a defined logic level)". 7. self refresh exit is asynchronous. 8. vref must be maintained during self refresh operation.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 52 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved clock enable (cke) truth table for synchronous transitions current state cke command (n) ras , cas , we , cs action (n) notes previous cycle current cycle power - down l l x maintain power - down 11, 13, 15 l h deselect or nop power - down exit 4, 8, 11, 13 self refresh l l x maintain self refresh 11, 15, 16 l h deselect or nop self refresh exit 4, 5, 9, 16 bank(s) active h l deselect or nop active power - down entry 4,8,10,11,13 all banks idle h l deselect or nop precharge pow er - down entry 4,8,10,11,13 h l autorefresh self refresh entry 6, 9, 11,13 any state other than listed above h h re fer to the command truth table 7 notes: 1. cke (n) is the logic state of cke at clock edge n; cke (n - 1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n. 3. command (n) is the com mand registered at clock edge n, and action (n) is a result of command (n). 4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. on self refresh exit deselect or nop commands must be issued on e very clock edge occurring during the txsnr period. r ead commands may be issued only after txsrd (200 clocks) is satisfied. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. v alid commands for power - down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselct only. 10. power - down and self refresh cannot be entered while read or write operations, (extended) mode register operations, prechar ge or refresh operations are in progress. see section 2.8 "power down" and section 2.7.2 "self refresh command" for a detailed list of restrictions. 11. minimum cke high time is 3 clocks, minimum cke low time is 3 clocks. 12. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 13. the power - down mode does not perform any refresh operations. the duration of power - down mode is therefore limited by the refresh requirements. 14. cke must be maintained hi gh while the device is in ocd calibration mode. 15. "x" means "don't care (including floating around vref)" in self refresh and power down. however dt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to "1" in mrs(1)). 16. vref must be maintained during self refresh operation
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 53 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved operating conditions absolute maximum dc ratings symbol parameter rating units notes v dd voltage on vdd pin relative to vss - 1.0 to + 2.3 v 1,3 v ddq voltage on vddq pin relative to vss - 0.5 to + 2.3 v 1,3 v ddl voltage on vddl pin relative to vss - 0.5 to + 2.3 v 1,3 v in , v out voltage on any pin relative to vss - 0.5 to + 2.3 v 1 ,4 t stg storage temperature - 55 to + 1 5 0 1,2 notes: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the op erational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended per iods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. 3. vdd and vddq mu s t be within 300mv of each other at all times; and vref must be not greater than 0.6 x vddq. when vdd and vddq and vddl are less than 500 mv, vref may be equal to or less than 300 mv. 4. voltage on any input or i/o may not exceed voltage on vddq. dram componen t operating temperature range symbol parameter grade rating units notes t oper operating temperature commercial 0 to 9 5 1 ,2 quasi industrial - 2 0 to 9 5 1,2 industrial - 4 0 to 9 5 1,2 automotive grade 2 - 40 to 105 1,2 automotive grade 3 - 40 to 95 1,2 not es: 1. operating temperature is the case surface temperature (tcase) on the center/top side of the dram. 2. if tc exceeds 85c , the dram must be refreshed externally at 2x refresh . i t is required to set tr e fi=3.9s in auto refres h mode and to set 1 for emrs (2) bit a7 in self refresh mode .
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 54 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved ac & dc operating conditions dc operating conditions recommended dc operating conditions (sstl_1 . 8) symbol parameter rating units notes min typ max v dd supply voltage 1.7 1.8 1.9 v 1 v dddl supply voltage for dll 1.7 1.8 1.9 v 5 v ddq supply voltage for output 1.7 1.8 1.9 v 1,5 v ref input reference voltage 0.49 * v ddq 0.5 * v ddq 0.51 * v ddq v 2, 3 v tt termination voltage v ref - 0.04 v ref v ref + 0.04 v 4 notes: 1. there is no specific device v dd supply voltage requirement for sstl_18 compliance. however under all conditions vddq must be less than or equal to vdd . 2. the value of vref may be selected by the user to provide optimum noise margin in the system. typically the value of vref is e xpected to be about 0.5 x vddq of the transmitting device and vref is expected to track variations in vddq. 3. peak to peak ac noise on vref may not exceed +/ - 2% vref (dc). 4. vtt is not applied directly to the device. vtt is a system supply for signal termination resi stors is expected to be set equal to vref and must track variations in die dc level of vref. 5. vddq tracks with vdd, vddl tracks with vdd. ac parameters are measured with vdd, vddq, and vddl tied together. odt dc electrical characteristic parameter / con dition symbol min nom max units notes rtt eff. impedance value for emrs(1)(a6,a2)=0,1; 75 rtt1(eff) 60 75 90 1 rtt eff. impedance value for emrs(1)(a6,a2)= 1 , 0 ; 150 rtt2(eff) 120 150 180 1 rtt eff. impedance value for emrs(1)(a6,a2)=1,1; 50 rtt3(eff) 40 50 60 1 deviation of vm with respect to vddq / 2 delta vm - 6 + 6 % 2 notes: 1. measurement definition for rtt(eff): 2. measurement definition for vm: v ih (ac) - v il (ac) i( v ih (ac) ) - i( v il (ac) ) rtt(eff) = vm = ( - 1 ) x 100% 2 x vm vddq
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 55 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved dc & ac logic input levels ddr2 sdram pin timing are specified for either single ended or differential mode depending on the setting of the emrs(1) enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timing are measured is mode dependent. in single ended mode, timing relationships are measured relative to th e rising or falling edges of dqs crossing at vref. in differential mode, these timing relationships are measured relative to the cross point of dqs and its complement, dqs. this distinction in timing methods is guaranteed by design and characterization . i n single ended mode, the dqs (and rdqs) signals are internally disabled and dont care. input dc logic level symbol parameter min max units v ih (dc) dc input logic high vref + 0.125 vddq + 0.3 v v il (dc) dc input logic low - 0.3 vref - 0.125 v input ac l ogic level symbol parameter ddr2 - 1066 ddr2 - 667, ddr2 - 800 units min max min max v ih ( a c) a c input logic high vref + 0.200 - vref + 0.200 vddq+vpeak v v il ( a c) a c input logic low - vref - 0.200 vssq - vpeak vref - 0.200 v note 1 refer to overshoot/undersh oot specifications for vpeak value: maximum peak amplitude allowed for overshoot and undershoot. ac input test conditions symbol condition value units notes v ref input reference voltage 0.5 x v ddq v 1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2,3 note 1 input waveform timing is referenced to the input signal crossing through the v ih/il(ac) level applied to the device under test. note 2 the input signal minimum slew rate is to be maintained over the range from v ref to v ih(ac) min for rising edges and the range from v ref to v il(ac) max for falling edges as shown in the below figure. note 3 ac timings are referenced with input waveforms switching from vil(ac) to vih(ac) on the positive transit ions and vih(ac) to vil(ac) on the negative transitions.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 56 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved differential input ac logic level symbol parameter min max units notes v id (ac) ac differential input voltage ddr2 - 667/800 0.5 vddq v 1,3 ddr2 - 1066 0.5 vddq + 0.6 1 v ix (ac) ac differentia l crosspoint voltage 0.5 x vddq - 0.175 0.5 x vddq + 0.175 v 2 no te 1 follow jedec 1066 specification (jesd208) note 2 v id (ac) specifies the input differential voltage |v tr - v cp | required for switching, where v tr is the true input signal (such as ck, dqs , ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to vih(ac) - vil(ac). note 3 the typical value of v ix (ac) is expected to be about 0.5 x vddq of the transmitting device and v ix (ac) is exp ected to track variations in vddq. v ix (ac) indicates the voltage at which differential input signals must cross. note 4 refer to overshoot/undershoot specifications for vpeak value: maximum peak amplitude allowed for overshoot an d undershoot. di fferential ac output parameters symbol parameter min max units notes v ox (ac) ac differential crosspoint voltage 0.5 x vddq - 0.125 0.5 x vddq + 0.125 v 1 note 1 the typical value of v ox( ac) is expected to be about 0.5 x vddq of the transmitting device a nd v ox (ac) is expected to track variations in vddq . v ox (ac) indicates the voltage at which differential output signals must cross.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 57 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved overshoot and undershoot specification ac overshoot / undershoot specification for address and control pins parameter ddr 2 - 1066 ddr2 - 800 ddr2 - 667 units maximum peak amplitude allowed for overshoot area 0.5(0.9) 1 0.5(0.9) 1 0.5(0.9) 1 v maximum peak amplitude allowed for undershoot area 0.5(0.9) 1 0.5(0.9) 1 0.5(0.9) 1 v maximum overshoot area above vdd 0.5 0.66 0.8 v / ns maximum undershoot area below vss 0.5 0.66 0.8 v / ns note 1 the maximum requirements for peak amplitude were reduced from 0.9v to 0.5v. ac overshoot / undershoot specification for clock, data, strobe and mask pins paramete r ddr2 - 1066 ddr2 - 800 ddr2 - 667 units maximum peak amplitude allowed for overshoot area 0.5 0.5 0.5 v maximum peak amplitude allowed for undershoot area 0.5 0.5 0. 5 v maximum overshoot area above vdd 0. 19 0. 23 0. 23 v / ns maximum undershoot area below vss 0. 19 0. 23 0. 23 v / ns vdd vss overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v) vddq vssq overshoot area undershoot area maximum amplitude maximum amplitude time (ns) volts (v)
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 58 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved power & ground clamp v - i characteristics power and ground clamps are provided on address, ras , cas , cs , we , cke, and odt pins. v - i characteristics for input - only pins with clamps voltage across clamp (v) minimum power clamp current minimum ground clamp current units 0.0 0.0 0.0 ma 0.1 0.0 0.0 ma 0.2 0.0 0.0 ma 0.3 0.0 0.0 ma 0.4 0.0 0.0 ma 0.5 0.0 0.0 ma 0.6 0.0 0.0 ma 0.7 0.0 0.0 ma 0.8 0.1 0.1 ma 0.9 1.0 1.0 ma 1.0 2.5 2.5 ma 1.1 4.7 4. 7 ma 1.2 6.8 6.8 ma 1.3 9.1 9.1 ma 1.4 11.0 11.0 ma 1.5 13.5 13.5 ma 1.6 16.0 16.0 ma 1.7 18.2 18.2 ma 1.8 21.0 21.0 ma
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 59 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved output buffer levels output ac test conditions symbol parameter sstl_18 units notes v otr output timing measurement reference level 0.5 x v ddq v 1 note 1 the vddq of the device under test is referenced.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 60 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved ocd default characteristics description parameter min nom max units notes output slew rate sout 1.5 - 5 v/ns 1 - 6 note 1 absolute specifications (toper; vdd = +1.8v 0.1v, vddq = +1.8v 0.1v). dram i/o specifications for timing, voltage, and slew rate are no longer applicable if ocd is changed from default settings. note 2 slew rate measured from vil(ac) to vih(ac). note 3 the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaranteed by design and characterization. note 4 dram output slew rate specification applies to 400 mt/s, 533 mt/s & 667 mt/s speed bins. note 5 timing skew due to dram output slew rate mis - match between dqs / dqs and associated dqs is included in tdqsq and tqhs specification. note 5 ddr2 sdram output slew rate test load is defined in the ac timing specification table.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 61 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved idd measurement conditions idd values are for fu ll operating range of voltage and temperature symbol parameter/condition idd0 operating one bank active - precharge current ; tck = tck(idd), trc = trc(idd), tras = trasmin(idd); cke is high, cs is high between valid commands; address bus inputs are switchi ng; data bus inputs are switching idd1 operating one bank active - read - precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), trc = trc (idd), tras = trasmin(idd), trcd = trcd(idd); cke is high, cs is high between valid commands; addr ess bus inputs are switching; data pattern is same as idd4w idd2p precharge power - down current ; all banks idle; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating idd2n precharge standby current ; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching idd2q precharge quiet standby current ; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 62 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved idd3p(0) active power - down current ; all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating mrs a12 bit is set to "0"( fast power - down exit); idd3p(1) active power - down curr ent ; all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating mrs a12 bit is set to "1"( slow power - down exit); idd3n active standby current ; all banks open; tck = tck(idd), tras = trasmax (idd), trp = trp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0 ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w idd4w operating burst write current ; all banks open, continuous burst wri tes; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching idd5 b burst refresh current ; tck = tck(idd); refresh co mmand at every trfc(idd) interval; cke is high, cs is high between valid commands;
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 63 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved other control and address bus inputs are switching; data bus inputs are switching idd6 self refresh current ; ck and ck at 0 v; cke 0.2 v; other control and address bus in puts are floating; data bus inputs are floating idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = trcd(idd) - 1 x tck(idd); tck = tck(idd), trc = trc(idd), trrd = trrd(idd), tfaw = tfaw(idd), trcd = 1 x tck(idd); cke is high, cs is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; - refer to the following pages for detailed timing conditions notes: 1. idd specifications are tested after the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs, rdqs, rdqs, ldqs, ldqs, udqs, and udqs. idd values must be met with all combinations of emrs bits 10 and 11 . 5. for ddr2 - 667/800 /1066 testing, tck in the conditions should be interpreted as tck(avg) 6. definitions for idd - low = vin vilac(max) - high = vin vihac(min) - stable = inputs stable at a high or low level - floating = inputs at vref = vddq/2 - switching = inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals, an d inputs changing between
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 64 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved idd testing parameters speed ddr2 - 1066 ddr2 - 800 ddr2 - 800 ddr2 - 667 units cl - trcd - trp 7 - 7 - 7 6 - 6 - 6 5 - 5 - 5 5 - 5 - 5 cl(idd) 7 6 5 5 tck trcd(idd) 13.125 15 12.5 15 ns trc(idd) 58.125 60 57.5 60 ns trrd(idd) C x8 7.5 7.5 7.5 7.5 n s trrd(idd) C x16 10 10 10 10 ns tfaw(idd) C x8 35 35 35 37.5 ns tfaw(idd) C x16 45 45 45 50 ns tck(idd) 1.875 2.5 2.5 3 ns trasmin(idd) 45 45 45 45 ns trasmax(idd) 70 k 70k 70 k 70 k ns trp(idd) 13.125 15 12.5 15 ns trfc(idd) 105 105 105 105 ns detailed idd7 legend: a = active; ra = read with autoprecharge; d = deselect idd7: operating current: all bank interleave read operation all banks are being interleaved at minimum trc(idd) without violating trrd(idd) and tfaw(idd) using a burst length of 4 . control and address bus inputs are stable during deselects. iout = 0 ma timing patterns for 4 bank devices with 1 kb or 2 kb page size - ddr2 - 667 5 - 5 - 5: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d - ddr2 - 667 4 - 4 - 4: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d - ddr2 - 800 6 - 6 - 6: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d d - ddr2 - 800 5 - 5 - 5: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d - ddr2 - 800 4 - 4 - 4: a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d - ddr2 - 1066 7 - 7 - 7: a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d d d d d - ddr2 - 1066 6 - 6 - 6: a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d d d d
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 65 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved idd specifications symbol x8 x16 unit ddr2 - 800 ddr2 - 1066 ddr2 - 800 ddr2 - 1066 typic al max typical max typical max typical max idd0 66 80 81 90 79 90 98 105 ma idd1 70 85 87 90 82 95 102 110 ma idd2p 7 12 7 12 7 12 7 12 ma idd2q 34 35 41 50 34 45 41 50 ma idd2n 42 50 51 60 42 50 51 60 ma idd3p0 27 45 30 50 36 55 40 60 ma idd3p1 1 2 25 12 25 20 40 20 40 ma idd3n 57 75 67 85 65 85 75 95 ma idd4w 135 170 167 220 165 185 202 230 ma idd4r 131 150 164 210 154 175 191 220 ma idd5b (trc = trfc) 101 110 128 135 100 120 127 135 ma idd5d (trc = trefi) 43 50 52 60 43 50 52 60 ma idd6 7 1 2 7 12 7 12 7 12 ma idd7 125 155 156 170 175 190 224 240 ma
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 66 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved input/output capacitance parameter symbol ddr2 - 1066 ddr2 - 800 ddr2 - 667 units min max min max min max input capacitance, ck and ck cck 1 .0 2 .0 1 .0 2 .0 1 .0 2 .0 pf input capacitance delta , ck and ck cdck x 0.25 x 0.25 x 0.25 pf input capacitance, all other input - only pins ci 1 .0 1.75 1 .0 1.75 1 .0 2 .0 pf input capacitance delta, all other input - only pins cdi x 0.25 x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 3.5 2 .5 3.5 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 x 0.5 pf refresh parameters parameter symbol 512 mb unit notes refresh to active/refresh command time trfc 10 5 ns 1 average periodic refresh interval tref i commercial 0 Q tcase Q 85 7.8 s 1 85 Q tcase Q 9 5 3.9 1,2,3 industrial - 40 Q tcase Q 8 5 7.8 1 85 Q tcase Q 9 5 3.9 1,2,3 quasi industrial - 2 0 Q tcase Q 8 5 7.8 1 85 Q tcase Q 9 5 3.9 1,2,3 automotive 2 - 40 Q tcase Q 8 5 7.8 1 85 Q tcase Q 10 5 3.9 1,2 ,3 automotive 3 - 40 Q tcase Q 8 5 7.8 1 85 Q tcase Q 9 5 3.9 1,2,3 note 1 if refresh timing is violated, data corruption may occur and the data must be re - written with valid data before a valid r ead can be executed. note 2 this is an additional featur e. for detailed information, please refer to operating temperature condition chapter in this spec note 3 when tc exceeds 85c, the dram must be refreshed externally at 2x refresh . i t is required to set tr e fi=3.9s in auto refresh mode and to set 1 for emrs (2) bit a7 in self refresh mode .
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 67 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 68 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved ac & dc operating conditions timing parameters (ddr2 - 1066 and ddr2 - 800) parameter symbol ddr2 - 1066 ddr2 - 800 units 34 notes min max min max clock cycle time tck 1875 7500 2500 8000 ps 35,36 ck high pulse width tch 0.48 0.52 0.48 0.52 tck(avg) 35,36 ck low pulse width tcl 0.48 0.52 0.48 0.52 tck(avg) 35,36 write command to dqs associated clock edge wl rl - 1 rl - 1 dqs latching rising transitions to associated clock edges tdqss - 0.25 0.25 - 0.25 0.25 tck(avg) 30 dqs falling edge to ck setup time tdss 0.2 - 0.2 - tck(avg) 30 dqs falling edge hold time from ck tdsh 0.2 - 0.2 - tck(avg) 30 dqs input high pulse width tdqsh 0.35 - 0.35 - tck(avg) dqs input low pulse width tdqsl 0.35 - 0.35 - tck(avg) write preamble twpre 0.35 - 0.35 - tck(avg) write postamble twpst 0.4 0.6 0.4 0.6 tck(avg) 10 address and control input setup time tis(base) 125 - 175 - ps 5,7,9,22 ,29 address and control input hold time tih(base) 200 - 250 - ps 5,7,9,23 ,29 control & address input pulse width for each input tipw 0.6 - 0.6 - tck(avg) dq and dm input setup time (differential strobe) tds(base) 0 - 50 - ps 6,7,8,20 ,28,31 dq and dm input hold time (differential strobe) tdh(base) 75 - 125 - ps 6,7,8,21 ,28,31 dq and dm i nput pulse width for each input tdipw 0.35 - 0.35 - tck(avg) dq output access time from ck, ck tac - 350 350 - 400 400 ps 40 dqs output access time from ck, ck tdqsck - 325 325 - 350 350 ps 40 data - out high - impedance time from ck, ck thz - tac,max - tac,max ps 18,40 dqs(/dqs) low - impedance time from ck, ck tlz(dqs) tac,min tac,max tac,min tac,max ps 18,40 dq low - impedance time from ck, ck tlz(dq) 2 x tac,min tac,max 2 x tac,min tac,max ps 18,40 dqs - dq skew for dqs and associated dq signals tdqsq - 175 - 200 ps 13 ck half pulse width thp min(tch(abs ),tcl(abs) ) - min(tch(abs ),tcl(abs) ) - ps 37 d q hold skew factor tqhs - 250 - 300 ps 38 dq/dqs output hold time from dqs tqh thp - tqhs - thp - tqhs - ps 39 read preamble trpre 0.9 1.1 0.9 1.1 tck(avg) 19,41
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 69 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved parameter symbol ddr2 - 1066 ddr2 - 800 units 34 notes min max min max read postamble trpst 0. 4 0.6 0.4 0.6 tck(avg) 19,42 active to active command period for 1kb page size trrd 7.5 - 7.5 ns 4,32 active to active command period for 2kb page size trrd 10 - 10 - ns 4,32 four activate window for 1kb page size tfaw 35 - 35 - ns 32 four activate wi ndow for 2 kb page size tfaw 4 5 - 4 5 - ns 32 cas to cas command delay tccd 2 - 2 - nck write recovery time twr 15 - 15 - ns 32 auto precharge write recovery + precharge time tdal wr+tnrp - wr+tnrp - nck 33 internal write to read command delay twtr 7.5 - 7.5 - ns 24,32 internal read to precharge command delay trtp 7.5 - 7.5 - ns 3,32 cke minimum pulse width (high and low pulse width) tcke 3 - 3 - nck 27 exit self refresh to a non - read command txsnr trfc + 10 - trfc + 10 - ns 32 exit self refresh to a read command txsrd 200 - 200 - nck exit precharge power down to any non - read command txp 2 - 2 - nck exit active power down to read command txard 2 - 2 - nck 1 exit active power down to read command (slow exit, lower power) txards 10 - al - 8 - al - nck 1,2 odt turn - on delay taond 2 2 2 2 nck 16 odt turn - on taon tac,min tac,max + 2.575 tac,min tacmax + 0.7 ns 6,16,40 odt turn - on (power - down mode) taonpd tac,min + 2 3 x tck(avg) +tac,max + 1 tac,min + 2 2 x tck(avg) +tac,max + 1 ns odt turn - off de lay taofd 2.5 2.5 2.5 2.5 nck 17,45 odt turn - off taof tac,min tac,max + 0.6 tac,min tac,max + 0.6 ns 17,43,4 5 odt turn - off (power - down mode) taofpd tac,min + 2 2.5 x tck(avg) + tac,max + 1 tac,min + 2 2.5 x tck(avg) + tac,max + 1 ns odt to power down e ntry latency tanpd 4 - 3 - nck odt power down exit latency taxpd 11 - 8 - nck mode register set command cycle time tmrd 2 - 2 - nck mrs command to odt update delay tmod 0 12 0 12 ns 32 ocd drive mode output delay toit 0 12 0 12 ns 32 minimum time c locks remains on after cke asynchronously drops low tdelay tis +tck(avg) +tih - tis +tck(avg) +tih - ns 15
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 70 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved ac & dc operating conditions timing parameters (ddr2 - 667) parameter symbol ddr2 - 667 units 34 notes min max clock cycle time tck 3000 8000 ps 35,36 ck high pulse width tch 0.48 0.52 tck(avg) 35,36 ck low pulse width tcl 0.48 0.52 tck(avg) 35,36 write command to dqs associated clock edge wl rl - 1 nck dqs latching rising transitions to associated clock edges tdqss - 0.25 0.25 tck(avg) 30 dqs falling edge to ck setup time tdss 0.2 - tck(avg) 30 dqs falling edge hold time from ck tdsh 0.2 - tck(avg) 30 dqs input high pulse width tdqsh 0.35 - tck(avg) dqs input low pulse width tdqsl 0.35 - tck(avg) write preamble twpre 0.35 - tck(avg) write postamble twpst 0.4 0.6 tck(avg) 10 address and control input setup time tis(base) 200 - ps 5,7,9,22,29 address and control input hold time tih(base) 275 - ps 5,7,9,23,29 control & address input pulse width for each input tipw 0.6 - tck(avg) d q and dm input setup time (differential strobe) tds(base) 100 - ps 6,7,8,20,28,31 dq and dm input hold time (differential strobe) tdh(base) 175 - ps 6,7,8,21,28,31 dq and dm input pulse width for each input tdipw 0.35 - tck(avg) dq output access time f rom ck, ck tac - 450 450 ps 40 dqs output access time from ck, ck tdqsck - 400 400 ps 40 data - out high - impedance time from ck, ck thz - tac,max ps 18,40 dqs( dqs ) low - impedance time from ck, ck tlz(dqs) tac,min tac,max ps 18,40 dq low - impedance time from ck , ck tlz(dq) 2 x tac,min tac,max ps 18,40 dqs - dq skew for dqs and associated dq signals tdqsq - 240 ps 13 ck half pulse width thp min(tch(abs),tcl (abs) ) - ps 37 dq hold skew factor tqhs - 340 ps 38 dq/dqs output hold time from dqs tqh thp - tqhs - ps 3 9 read preamble trpre 0.9 1.1 tck(avg) 19,41 read postamble trpst 0.4 0.6 tck(avg) 19,42 active to active command period for 1kb page size trrd 7.5 - ns 4,32 active to active command period for 2kb page size trrd 10 - ns 4,32 four activate window for 1kb page size tfaw 37.5 - ns 32 four activate window for 2 kb page size tfaw 50 - ns 32
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 71 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved parameter symbol ddr2 - 667 units 34 notes min max cas to cas command delay tccd 2 - nck write recovery time twr 15 - ns 32 auto precharge write recovery + precharge time tdal wr + tnrp - nck 33 internal write to read command delay twtr 7.5 - ns 24,32 internal read to precharge command delay trtp 7.5 - ns 3,32 cke minimum pulse width(high and low pulse width) tcke 3 - nck 27 exit self refresh to a non - read command txsnr trfc + 10 - ns 32 exit self refresh to a read command txsrd 200 - nck exit precharge power down to any non - read command txp 2 - n ck exit active power down to read command txard 2 - nck 1 exit active power down to read command (slow exit, lower power) txards 7 - al - nck 1,2 odt turn - on delay taond 2 2 nck 16 odt turn - on taon tac,min tac max + 0.7 ns 6,16,40 odt turn - on (power - d own mode) taonpd tac,min + 2 2 x tck(avg) +tac,max + 1 ns odt turn - off delay taofd 2.5 2.5 nck 17,45 odt turn - off taof tac,min tac,max + 0.6 ns 17,43,45 odt turn - off (power - down mode) taofpd tac,min + 2 2.5 x tck(avg) + tac,max + 1 ns odt to power do wn entry latency tanpd 3 - nck odt power down exit latency taxpd 8 - nck mode register set command cycle time tmrd 2 - nck mrs command to odt update delay tmod 0 12 ns 32 ocd drive mode output delay toit 0 12 ns 32 minimum time clocks remains on af ter cke asynchronously drops low tdelay tis +tck(avg) +tih - ns 15
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 72 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved general notes, which may apply for all ac parameters general note 1 ddr2 sdram ac timing reference load the figure represents the timing reference load used in defining the relevant tim ing parameters of the device. it is not intended to either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. system designers should use ibis or other simulation tools to correlat e the timing reference load to a system environ ment. manufacturers correlate to their production test conditions, generally a coaxial transmission line terminated at the tester electronics. this referen ce load is also used for output slew rate characteriz ation. the output timing reference voltage level for single ended signals is the cross point with vtt. the output timing reference voltage level for differential signals is the cross point of the true (e.g. dqs ) and the complement (e.g. dqs ) signal. general note 2 slew rate measurement levels a) output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs - dqs ) output slew rate is measured bet ween dqs - dqs = - 500mv and dqs - dqs = + 500 mv. output slew rate is guaranteed by design, but is not necessarily tested on each device. b) input slew rate for single ended signals is measured from vref(dc) to vih(ac),min for rising edges and from vref(d c) to vil(ac),max for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = - 250 mv to ck - ck = + 500 mv (+ 250 mv to - 500 mv for falling edges). c) vid is the magnitude of the difference between th e input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. general note 3 ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as following
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 73 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved general note 4 differentia l data strobe ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the d dr2 sdram pin timings are measured is mode dependent. in single ended mode, timing relationships are measured relative to the rising or falling edges of dqs crossing at vref . in differential mode, these timing relationships are measured relative to the cro ss point of dqs and its complement, dqs . this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss thro ugh a 20 to 10 k resistor to insure proper operation. general note 5 ac timings are for linear signal transitions. see specific notes on derating for other signal transitions. general note 6 all voltages are referenced to vss. general note 7 these p arameters guarantee device behavior, but they are not necessarily tested on each device.. general note 8 tests for ac timing, idd, and electrical (ac and dc) characteristics, may be conducted at nominal reference/supply voltage levels, but the related spec ifications and device operation are guaranteed for the full voltage range specified.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 74 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved specific notes for dedicated ac parameters specific note 1 user can choose which active power down exit timing to use via mrs (bit 12). txard is expected to be used for f ast active power down exit timing. txards is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet. specific note 2 al = additive latency. specific note 3 this is a minimum requirement. mi nimum read to precharge timing is al + bl / 2 provided that the trtp and tras(min) have been satisfied. specific note 4 a minimum of two clocks (2 x tck or 2 x nck) is required irrespective of operating frequency. specific note 5 timings are specified with command/address input slew rate of 1.0 v/ns. see specific notes on derating for other slew rate values. specific note 6 timings are specified with dqs, dm, and dqss (dqs/rdqs in single ended mode) input slew rate of 1.0v/ns. see specific notes on deratin g for other slew rate values. specific note 7 t imings are specified with ck/ ck differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1 v/ns in single ended mode. see specific notes on derating for other slew rate values. s pecific note 8 data setup and hold time derating.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 75 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved tds/tdh derating with differential data strobe ( ddr2 - 1066 , ddr2 - 800, ddr2 - 667) tds, tdh d erating v alues ( u nits : ps ) dqs , dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/n s 1.2 v/ns 1.0 v/ns 0 . 8 v/ns t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h t d s t d h dq slew rate ( v/ns ) 2 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 - - - - - - - - - - 1 0 0 0 0 0 0 1 2 12 24 24 - - - - - - - - 0.9 - - - 5 - 14 - 5 - 14 7 - 2 19 10 31 22 - - - - - - 0.8 - - - - - 13 - 31 - 1 - 19 11 - 7 23 5 35 17 - - - - 0.7 - - - - - - - 10 - 42 2 - 30 14 - 18 26 - 6 38 6 - - 0.6 - - - - - - - - - 10 - 59 2 - 47 14 - 35 26 - 23 38 - 11 0.5 - - - - - - - - - - - 24 - 89 - 12 - 77 0 - 65 12 - 53 0.4 - - - - - - - - - - - - - 52 - 140 - 40 - 128 - 28 - 116 for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base ) and tdh(base) value to the tds and tdh derating value respectively. example: tds (total setup time) = tds(base) + tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vih(ac)min. setup ( tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded v ref(dc) to ac region , use nominal slew rate for derating value . if the actual signal is later than the nominal slew rate line anywhere between shaded v ref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for dera ting value . hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of v ref(dc) . hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the l ast crossing of vih(dc)min and the first crossing of v ref(dc) . if the actual signal is always later than the nominal slew rate line between shaded dc level to v ref(dc) region, use nominal slew rate for derating value (see figure 79 for differential data strobe.) if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to v ref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value . although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach v ih/il (ac). t he derating values may be obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 76 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration of nominal slew rate for tds (differential dqs, dqs
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 77 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration of nominal slew rate for tds (single - ended dqs) note 1 dqs signal must be monotonic between vil(dc)max and vih(dc)min.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 78 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration of tangent line for tds (differential dqs, dqs
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 79 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration of tangent line for tds (single - ended dqs) note dqs signal must be monotonic between vil(dc)max and vih(dc)min.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 80 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration of nominal slew rate for tdh (differential dqs, dqs
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 81 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration of nominal slew rate for tdh (single - ended dqs) note dqs signal must be monotonic between v il(dc)max and vih(dc)min.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 82 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration tangent line for tdh (differential dqs, dqs
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 83 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration tangent line for tdh (single - ended dqs) note dqs signal must be monotonic between vil(dc)max and vih(dc)min.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 84 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved specific note 9 tis and tih (input se tup and hold) derating t i s/t i h derating with differential data strobe ( ddr2 - 1066 , ddr2 - 800, ddr2 - 667) t i s, t i h d erating v alues command address slew rate ( v/ns) ck, ck differential slew rate units 2.0 v/ns 1.5 v/ns 1.0 v/ns tis tih tis tih t is tih 4.0 0 150 94 180 124 210 154 ps 3.5 0 143 89 173 119 203 149 ps 3.0 0 133 83 163 113 193 143 ps 2.5 0 120 75 150 105 180 135 ps 2.0 0 100 45 130 75 160 105 ps 1.5 0 67 21 97 51 127 81 ps 1.0 0 0 0 30 30 60 60 ps 0.9 0 - 5 - 14 25 16 55 46 ps 0.8 0 - 13 - 31 17 - 1 47 29 ps 0.7 0 - 22 - 54 8 - 24 38 6 ps 0.6 0 - 34 - 83 - 4 - 53 26 - 23 ps 0.5 0 - 60 - 125 - 30 - 95 0 - 65 ps 0.4 0 - 100 - 188 - 70 - 158 - 40 - 128 ps 0.3 0 - 168 - 292 - 138 - 262 - 108 - 232 ps 0.25 - 200 - 375 - 170 - 345 - 140 - 315 ps 0.20 - 325 - 500 - 295 - 470 - 265 - 440 ps 0.15 - 517 - 708 - 487 - 678 - 457 - 648 ps 0.10 - 1000 - 1125 - 970 - 1095 - 940 - 1065 ps for all input signals the total tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis(base ) and tih(base) val ue to the tis and tih derating value respectively. example: tis (total setup time) = tis(base) + tis setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vih(ac)min . setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded v ref(dc) to ac region, use nominal slew rate for derating value (see figure 81). if the actual signal is later than the nominal slew rate line anywhere between shaded v ref(dc) to ac region, the slew rate of a tangent line to the actual signal from the ac level to d c level is used for derating value. hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of v ref(dc) or the last crossing of vih(dc)min and the first crossing of v ref(dc ) . if the actual signal is always later than the nominal slew rate line between shaded dc to v ref(dc) region, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to v ref(dc ) region, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value. although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach v ih/il (ac). for slew rates in between the values listed , the derating values may obtained by linear interpolation. these values are typi cally not subject to production test. they are verified by design and characterization.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 85 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration of nominal slew rate for tis
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 86 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration of tangent line for tis
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 87 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration of nominal slew rate for tih
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 88 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved illustration tangent line for tih
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 89 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved specific note 10 the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. specific note 11 min ( tcl, tch) refers to t he smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch).for exa mple, tcl and tch are = 50% of the period, less the half period j itter ( tjit(hp)) of the clock source, and less the half period jitter due to crosstalk ( tjit(crosstalk)) into the clock traces. specific note 12 tqh = thp C tqhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on - chip clock circuits; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p - channel to n - channel variation of the output drivers. specific note 13 tdqsq: consists of data pin skew and output pattern effects, and p - channel to n - channel variation of the output drivers as well as ou tput slew rate mismatch between dqs / dqs and associated dq in any given cycle. specific note 14 tdal = wr + ru{ trp[ns] / tck[ns] }, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for trp, if the result of the division is not already an integer,round up to the next highest integer. tck refers to the application clock period. example: for ddr533 at tck = 3.75ns with wr programmed to 4 clocks. tdal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. specific note 15 t he clock frequency is allowed to change during self C refresh mode or precharge power - down mode. in case of clock frequency change during precharge power - down, a specific procedure is required. specific note 16 odt turn on time min is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measured from taond, which is interpreted differently per speed bin. for ddr2 - 667/800, taond is 2 clock cycles after the clock edge t hat registered a first odt high counting the actual input clock edges. specific note 17 odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance. both are measured from taofd, wh ich is interpreted differently per speed bin. for ddr2 - 667/800, if tck(avg) = 3 ns is assumed, taofd is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first odt low and by counting the actual input clock edges. specific note 18 thz and tlz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (thz), or begins driving (tlz) .the following figure shows a method to calculate the point when device is no longer driving (thz), or begins driving (tlz) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calc ulation is consistent. tlz(dq) refers to tlz of the dqs and tlz(dqs) refers to tlz of the (u/l/r)dqs and ?u?l?r?dqs each treated as single - ended signal.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 90 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved specific note 19 trpst end point and trpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (trpst), or begins driving (trpre). the following figure shows a method to calculate these points when the device is no longer driving (trpst), or begins driving (trpre) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. specific note 20 input waveform timing tds with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at the vih(ac) level to the differential data strobe crosspoint for a rising signal, and from the inpu t signal crossing at the vil(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs, dqs? signals must be monotonic between vil(dc)max and vih(dc)min. specific note 21 input waveform timing tdh with d ifferential data strobe enabled mr[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing at the vih(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the vil(dc) level for a rising signal applied to the device under test. dqs, ?dqs? signals must be monotonic between vil(dc)max and vih(dc)min.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 91 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved specific note 22 input waveform timing is referenced from the input signal crossing at the vih(ac) level for a rising signal and vil(ac) for a falling signal applied to the device under t est. specific note 23 input waveform timing is referenced from the input signal crossing at the vil(dc) level for a rising signal and vih(dc) for a falling signal applied to the device under test. specific note 24 twtr is at lease two clocks (2 x tck or 2 x nck) independent of operation frequency. specific note 25 input waveform timing with single - ended data strobe enabled mr[bit10] = 1, is referenced from the input signal crossing at the vih(ac) level to the single - ended data strobe crossing vih/l(dc) at the start of its transition for a rising signal, and from the input signal crossing at the vil(ac) level to the single - ended data strobe crossing vih/l(dc) at the start of its transition for a falling signal applied to the device under test. the dqs signa l must be monotonic between vil(dc)max and vih(dc)min. specific note 26 input waveform timing with single - ended data strobe enabled mr[bit10] = 1, is referenced from the input signal crossing at the vih(dc) level to the single - ended data strobe crossing vi h/l(ac) at the end of its transition for a rising signal, and from the input signal crossing at the vil(dc) level to the single - ended data strobe crossing vih/l(ac) at the end of its transition for a falling signal applied to the device under test. the dqs signal must be monotonic between vil(dc)max and vih(dc)min. specific note 27 tckemin of 3 clocks means cke must be registered on three consecutive positive clock edges.cke must remain at the valid input level the entire time it takes to achieve the 3 cloc ks of registration. thus, after any cke transition, cke may not transition from its valid level during the time period of tis + 2 x tck + tih. specific note 28 if tds or tdh is violated, data corruption may occur and the data must be re - written with valid data before a valid read can be executed. specific note 29 these parameters are measured from a command/address signal ( cke , cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to t he clock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter is present or not. specific note 30 these parameters are measured from a data strobe signal ((l/u/r)dqs/ dqs ) crossing to its respective clock signal (ck/ ck ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is pres ent or not. specific note 31 these parameters are measured from a data signal ((l/u)dm, (l/u)dq0, (l/u)dq1, etc.) transition edge to its respective data strobe signal ((l/u/r)dqs/ dqs ) crossing. specific note 32 for these parameters, the ddr2 sdram device i s characterized and verified to support
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 92 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved tnparam = ru{tparam / tck(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. for example, the device will support tnrp = ru{trp / tck(avg)}, which is in clock cycles, if al l input clock jitter specifications are met. this means: for ddr2 - 667 5 - 5 - 5, of which trp = 15ns, the device will support tnrp =ru{trp / tck(avg)} = 5, i.e. as long as the input clock jitter specifications are met, precharge command at tm and a ctive comman d at tm+5 is valid even if (tm+5 - tm) is less than 15ns due to input clock jitter. specific note 33 tdal [nck] = wr [nck] + tnrp [nck] = wr + ru {trp [ps] / tck(avg) [ps] }, where wr is the value programmed in the mode register set. ex) for ddr2 - 1066 7 - 7 - 7 at tck(avg) = 1.875 ns with wr programmed to 8 nck, tdal = 8 + ru{13.125 ns / 1.875 ns} [nck] = 8 + 7 [nck] = 15 [nck] specific note 34 new units, tck(avg) and nck, are introduced in ddr2 - 667 , ddr2 - 800 and ddr2 - 1066 unit tck(avg) represents the ac tual tck(avg) of the input clock under operation. unit nck represents one clock cycle of the input clock, counting the actual clock edges. ex) txp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm+2,even i f (tm+2 - tm) is 2 x tck(avg) + terr(2per),min. ex) txp = 3 [nck] means; if power down exit is registered at tm, an active command may be registered at tm+3, even if (tm+3 - tm) is 3 x tck(avg) + terr(3per),min.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 93 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved specific note 35 input clock jitter spec pa rameter. these parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply. the jitter specified is a random jitter meeting a gaussian distribution. input clock jitter spec parameter apply p arameter symbol ddr2 - 1066 ddr2 - 800 ddr2 - 667 units min max min max min max clock period jitter tjit(per) - 90 90 - 100 100 - 125 125 ps clock period jitter during dll locking period tjit(per,lck) - 80 80 - 80 80 - 100 100 ps cycle to cycle clock period jit ter tjit(cc) - 180 180 - 200 200 - 250 250 ps cycle to cycle clock period jitter during dll locking period tjit(cc,lck) - 160 160 - 160 160 - 200 200 ps cumulative error across 2 cycles terr(2per) - 132 132 - 150 150 - 175 175 ps cumulative error across 3 cycles terr(3per) - 157 157 - 175 175 - 225 225 ps cumulative error across 4 cycles terr(4per) - 175 175 - 200 200 - 250 250 ps cumulative error across 5 cycles terr(5per) - 188 188 - 200 200 - 250 250 ps cumulative error across n cycles,n = 6 ... 10, inclusive terr(6 - 10per) - 250 250 - 300 300 - 350 350 ps cumulative error across n cycles,n = 11 ... 50, inclusive terr(11 - 50per) - 425 425 - 450 450 - 450 450 ps duty cycle jitter tjit(duty) - 75 75 - 100 100 - 125 125 ps definitions: - tck(avg) tck(avg) is calculated as the average clock period across any consecutive 200 cycle window. - tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. tcl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 94 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved - tjit(duty) tjit(duty) is defined as the cumulative set of tch jitter and tcl jitter. tch jitter is the largest deviation of any single tch from tch(avg). tcl jitter is the largest deviation of any sing le tcl from tcl(avg). tjit(duty) = min/max of {tjit(ch), tjit(cl)} where, tjit(ch) = {tchi - tch(avg) where i=1 to 200} tjit(cl) = {tcli - tcl(avg) where i=1 to 200} - tjit(per), tjit(per,lck) tjit(per) is defined as the largest deviation of any single tck from tck(avg). tjit(per) = min/max of {tcki - tck(avg) where i=1 to 200} tjit(per) defines the single period jitter when the dll is already locked. tjit(per,lck) uses the same definition for single period jitter, during the dll locking period only. tjit(per ) and tjit(per,lck) are not guaranteed through final production testing. - tjit(cc), tjit(cc,lck) tjit(cc) is defined as the difference in clock period between two consecutive clock cycles: tjit(cc) = max of |tcki+1 C tcki| tjit(cc) defines the cycle to c ycle jitter when the dll is already locked. tjit(cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not guaranteed through final production testing. - terr(2per), terr (3per), terr (4per), terr (5per), terr (6 - 10per) and terr (11 - 50per) terr is defined as the cumulative error across multiple consecutive cycles from tck(avg).
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 95 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved specific note 36 these parameters are specified per their average values, however it is understood th at the following relationship between the average timing and the absolute instantaneous timing holds at all times. ( m in and max of spec values are to be used for calculations in the table below.) example: for ddr2 - 667, tch(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps specific note 37 thp is the minimum of the absolute half period of the actual input clock. thp is an in put parameter but not an input specification parameter. it is used in conjunction with tqhs to derive the dram output timing tqh. the value to be used for tqh calculation is determined by the following equation; thp = min ( tch(abs), tcl(abs) ), where, tch (abs) is the minimum of the actual instantaneous clock high time; tcl(abs) is the minimum of the actual instantaneous clock low time; specific note 38 tqhs accounts for: 1) the pulse duration distortion of on - chip clock circuits, which represents how well the actual thp at the input is transferred to the output; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pat tern effects, and p - channel to n - channel variation of the output drivers specific note 39 tqh = thp C tqhs, where: thp is the minimum of the absolute half period of the actual input clock; and tqhs is the specification value under the max c olumn. {the less half - pulse width distortion present, the larger the tqh value is; and the larger the valid data eye will be.} examples: 1) if the system provides thp of 1315 ps into a ddr2 - 667 sdram, the dram provides tqh of 975 ps minimum. 2) if the system provides thp of 1420 ps into a ddr2 - 667 sdram, the dram provides tqh of 1080 ps minimum. 3 ) if the system provides thp of 825 ps into a ddr2 - 1066 sdram, the dram provides tqh of 575 ps minimum. 4 ) if the system provides thp of 900 ps into a ddr2 - 1066 sdram, the dram pr ovides tqh of 650 ps minimum. specific note 40 when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(6 - 10per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2 - 667 sdram has terr(6 - 10per),min = - 272 ps and terr(6 - 10per),max = + 293 ps, then tdqsck,min(derated) = tdqsck,min - terr(6 - 10per),max = - 400 ps - 293 ps = - 693 ps and tdqsck,max(derated) = tdqsck,max - terr(6 - 10per),min = 400 ps + 272 ps = + 672 ps. similarly, tlz(dq) for ddr2 - 667 derates to tlz(dq),min(derated) = - 900 ps - 293 ps = - 1193 ps and tlz(dq),max(derated)= 450 ps + 272 ps = + 722 ps. (caution on the min/max usage!) parameter symbol min max units absolute clock period tck(ab s) tck(avg),min + tjit(per),min tck(avg),max + tjit(per),max ps absolute clock high pulse width tch(abs) tch(avg),min x tck(avg),min +tjit(duty),min tch(avg),max x tck(avg),max + tjit(duty),max ps absolute clock low pulse width tcl(abs) tcl(avg),min x tc k(avg),min + tjit(duty),min tcl(avg),max x tck(avg),max + tjit(duty),max ps
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 96 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved specific note 41 when the device is operate d with input clock jitter, this parameter needs to be derated by the actual tjit(per) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2 - 667 sdram has tjit(per),min = - 72 ps and tj it(per),max = + 93 ps, then trpre,min(derated) = trpre,min + tjit(per),min = 0.9 x tck(avg) - 72 ps = + 2178 ps and trpre,max(derated) = trpre,max + tjit(per),max = 1.1 x tck(avg) + 93 ps = + 2843 ps. (caution on the min/max usage!) specific note 42 when t he device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(duty) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2 - 667 sdram has tjit(duty ),min = - 72 ps and tjit(duty),max = + 93ps, then trpst,min(derated) = trpst,min + tjit(duty),min = 0.4 x tck(avg) - 72 ps = + 928 ps and trpst,max(derated) = trpst,max + tjit(duty),max = 0.6 x tck(avg) + 93 ps = + 1592 ps. (caution on the min/max usage!) specific note 43 when the device is operated with input clock jitter, this parameter needs to be derated by { - tjit(duty),max - terr(6 - 10per),max } and { - tjit(duty),min - terr(6 - 10per),min } of the actual input clock.(output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2 - 667 sdram has terr(6 - 10per),min = - 272 ps, terr(6 - 10per),max = + 293 ps, tjit(duty),min = - 106 ps and tjit(duty),max = + 94 ps, then taof,min(derated) = taof,min+ { - tjit(duty),max - t err(6 - 10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and taof,max(derated) =taof,max + { - tjit(duty),min - terr(6 - 10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps. (caution on the min/max usage!) specific note 44 for taofd of ddr2 - 667/80 0, the 1/2 clock of nck in the 2.5 x nck assumes a tch(avg),average input clock high pulse width of 0.5 relative to tck(avg). taof,min and taof,max should each be derated by the same amount as the actual amount of tch(avg) offset present at the dram input with respect to 0.5. for example, if an input clock has a worst case tch(avg) of 0.48, the t aof,min should be derated by subtracting 0.02 x tck(avg) from it, whereas if an input clock has a worst case tch(avg) of 0.52, the taof,max should be derated by add ing 0.02 x tck(avg) to it. therefore, we have; taof,min(derated) = tac,min - [0.5 - min(0.5, tch(avg),min)] x tck(avg) taof,max(derated) = tac,max + 0.6 + [max(0.5, tch(avg),max) - 0.5] x tck(avg) or taof,min(derated) = min(tac,min, tac,min - [0.5 - tch(av g),min] x tck(avg)) taof,max(derated) = 0.6 + max(tac,max, tac,max + [tch(avg),max - 0.5] x tck(avg)) where tch(avg),min and tch(avg),max are the minimum and maximum of tch(avg) actually measured at the dram input balls. note that these deratings are in ad dition to the taof derating per input clock jitter, i.e. tjit(duty) and terr(6 - 10per). however tac values used in the equations shown above are from the timing parameter table and are not derated. thus the final derated values for taof are; taof,min(derate d_final) = taof,min(derated) + { - tjit(duty),max - terr(6 - 10per),max } taof,max(derated_final) = taof,max(derated) + { - tjit(duty),min - terr(6 - 10per),min }
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 97 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved revision history version page modified description released 1.0 all - preliminary release . 0 8 / 20 13 1.1 all - official release. 01/2014 1.2 p1,2,13 cl2 remove cl2 function. 03/2014 1.3 p64 idd x update x16 ddr2 - 800 iddx values . 05/2014 1.4 p 3 ordering information add part number: nt5 tu32m16eg - aca and nt5tu32m16eg - ach . 06/2014 p4 part number ing guide simplify part numbering guide. p1,52,65 temperature spec add temperature range 1. automotive grade 2 ( - h ) = - 40 to + 105 2. automotive grade 3 ( - a ) = - 40 to + 9 5 p64 idd specifications modify x8 ddr2 - 800/1066 idd spec. 1.5 p52 absolute maximum dc ratings update tstg specification: - 55 ~150 (was: - 55 ~100) 06/2015 1.6 p1 - 5,53,66 - 1. add quasi industria l grade part number and temperature range. 2. add s peed and voltage compatibility . 08/2015 p5 - 7 - package naming : vfbga (was: bg a) p64 idd testing parameters 1. add ddr2 - 800 6 - 6 - 6 c ondition . 2. remove ddr2 - 1066 6 - 6 - 6 condition.
ddr2 512 mb sdram nt5tu 64 m8 e e / nt5tu 32 m16 e g 98 ver sion 1. 6 nanya technology corp. ? 0 8 /201 5 all rights reserved http://www.nanya.com/

▲Up To Search▲

Price & Availability of NT5TU32M16EG-BE

	To Download NT5TU32M16EG-BE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .